Connecting IP Blocks to Create a Complete System - Connecting IP Blocks to Create a Complete System - 2025.2 English - UG1305

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

Document ID
UG1305
Release Date
2025-12-09
Version
2025.2 English

To connect IP blocks to create a system, follow these steps.

  1. Double-click the Versal CIPS IP core.

  2. Click PS-PMC→ PS-PL Interfaces.

  3. Enable the M_AXI_FPD interface and set the Number of PL Resets to 1, as shown in the Image.

    ../_images/PS_PL_Interfaces.png
  4. Click Clocking, and then click on the Output Clocks tab.

  5. Expand PMC Domain Clocks. Then expand PL Fabric Clocks. Configure the PL0_REF_CLK to 300 MHz as shown in the following figure:

    ../_images/clocking_ps_PMC.png
  6. Click OK and Finish to complete the configuration and return to the block diagram.