Configuring Your Design - Configuring Your Design - 2025.2 English - UG1305

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

Document ID
UG1305
Release Date
2025-12-09
Version
2025.2 English

To configure your design, follow these steps:

  1. Open the design created in Creating a New Embedded Project with Versal Devices, edt_versal.xpr.

  2. Open the block design, edt_versal.bd.

  3. Add AXI NoC IP from the IP catalog.

  4. Click Run Block Automation.

  5. Make the run block settings as shown in the following figure:

    ../_images/block-auto1.png
  6. Open CIPS → PS-PMC.

  7. Click NoC. Enable the NoC Non-Coherent Interfaces PS to NoC Interface 0/1 as shown below.

    ../_images/noc-interface.png
  8. Click OK and Finish to complete and exit CIPS configuration.

  9. Double-click the NoC IP. From the General Tab, set Number of AXI Slave interfaces and AXI Clocks to 8:

    ../_images/noc-settings.png
  10. From the Inputs tab, configure the following settings for S06 AXI and S07 AXI:

../_images/noc-axi.png
  1. Configure the following settings from the Connectivity tab:

    ../_images/noc-connectivity.png
  2. Click OK.

  3. Make connections between CIPS and NoC as shown below

    ../_images/noc-ip-1.png

    This adds the AXI NoC IP for DDR access.

    ../_images/noc-ip.png