Configuring PL Hardware - Configuring PL Hardware - 2025.2 English - UG1305

Versal Adaptive SoC Embedded Design Tutorial (UG1305)
Document ID
UG1305
Release Date
2025-12-09
Version
2025.2 English

To configure the PL IPs used in this design example, follow these steps.

  1. Right-click the block diagram and select Add IP from the IP catalog.

  2. Search for AXI GPIO and double-click the AXI GPIO IP to add four instance of IP into the design.

  3. Search for AXI Uartlite in the IP catalog and add it into the design.

  4. Click Run Connection Automation in the Block Design view.

    ../_images/image62.png

    The Run Connection Automation dialog box opens.

  5. In the Run Connection Automation dialog box, select the All Automation check box.

    ../_images/vpk_image63.png

    This checks the automation for all the ports of the AXI GPIO IP.

  6. Click GPIO of axi_gpio_0 and set the Select Board Part Interface to Custom as shown below.

    ../_images/vpk_image64.png

  7. Click S_AXI of axi_gpio_0. Set the configurations as shown in the following figure.

    ../_images/vpk_gpio_config0.png

  8. Repeat steps 6 and 7 for axi_gpio_1, axi_gpio_2, and axi_gpio_3.

  9. Click S_AXI of axi_uartlite_0. Set the configurations as shown in the following figure.

    ../_images/vpk_s-axi-uartlite1.png

  10. Click UART of axi_uartlite_0. Set the configurations as shown in the following figure.

../_images/vpk_s-axi-uartlite.png

  1. Click OK.

  2. This configuration sets the following connections:

    • Connects the S_AXI of AXI_GPIO and AXI UART lite to M_AXI_FPD of CIPS with SmartConnect as a bridge IP between CIPS and AXI GPIO IPs.

    • Enables the processor system reset IP.

    • Connects the pl0_ref_clk to the processor system reset, AXI GPIO, and the SmartConnect IP clocks.

    • Connects the reset of the SmartConnect and AXI GPIO to the peripheral_aresetn of the processor system reset IP.

  3. Click Run Connection Automation in the block design window and select the All Automation check box.

  4. Click ext_reset_in and configure the setting as shown below.

../_images/ch7_image66.jpeg

This connects the ext_reset_in of the processor system reset IP to the pl_resetn of the CIPS.

  1. Click OK.

  2. Disconnect the aresetn of SmartConnect IP from peripheral_aresetn of processor system reset IP.

  3. Connect the aresetn of SmartConnect IP to interconnect_aresetn of processor system reset IP.

../_images/image67.jpeg

  1. Double-click the axi_gpio_0 IP to open it.

  2. Go to the IP Configuration tab, and configure the settings as shown in the following figure.

../_images/vpk_image68.png

  1. Make the same setting for axi_gpio_1, axi_gpio_2, and axi_gpio_3.

  2. Delete the external pins of the axi_gpio_0 IP and expand the interface.

  3. Make the output of axi_gpio_0 IP as External.

  4. Right-click the external port of axi_gpio_0 IP and select External Port Properties and rename as Dout_0.

../_images/vpk_gpio_port.png

  1. Repeat step 21 to step 23 for axi_gpio_1, axi_gpio_2, and axi_gpio_3 and rename as Dout_1, Dout_2, and Dout_3, respectively.

  2. Add three instances of AXI Register Slice IP to be placed on SLR-1, SLR-2, and SLR-3.

  3. Right-click a Register Slice IP and select Block Properties and rename as axi_register_slice_1_s2 as shown below.

../_images/vpk_register_light_2.png

  1. Double-click the AXI Register Slice IP, and set Protocol as AXI4LITE by setting it as manual as shown below.

../_images/vpk_register_light_1.png

  1. Repeat step 26 and 27 for the second and third instances of AXI Register Slice IP and rename as axi_register_slice_2_s2 and axi_register_slice_3_s2, respectively.

Note

axi_register_slice_1_s2, axi_register_slice_2_s2, and axi_register_slice_3_s2 are placed to SLR-1, SLR-2, and SLR-3, respectively using the constraints file provided as part of the package in the ``pl_gpio_uart/constrs` folder.

SLR Crossing from SLR-0 to SLR-1

Note

SLR crossing registers are added to improve timing closure and alleviate routing congestion of long resources.

  1. Add two instances of AXI Register Slice IP to handle the SLR crossing from SLR-0 to SLR-1.

  2. Right-click the Register Slice IP and select Block Properties and rename as axi_register_slice_1_s1.

  3. Double-click the Register Slice IP and set the Register Slice Option as SLR Crossing as shown below.

    ../_images/vpk_slr_crossing_1.png

  4. Repeat step 30 and step 31 for the second instance of AXI Register Slice IP and rename as axi_register_slice_1_s3.

SLR Crossing from SLR-0 to SLR-2

  1. Similarly add two instances of AXI Register Slice IP to handle the multi SLR crossing from SLR-0 to SLR-2.

  2. Right-click a Register Slice IP and select Block Properties and rename as axi_register_slice_2_s1.

  3. Double-click a Register Slice IP and set the Register Slice Option as Multi SLR Crossing as shown below.

    ../_images/vpk_multi_slr_crossing_2_1.png

  4. Open SLR Crossing tab, and set Number of SLR Crossing as 2 as shown below.

    ../_images/vpk_multi_slr_crossing_2_2.png

  5. Repeat step 34, step 35, and step 36 for the second instance of AXI Register Slice IP and rename as axi_register_slice_2_s3.

SLR Crossing from SLR-0 to SLR-3

  1. Similarly add two instances of AXI Register Slice IP to handle the SLR crossing from SLR-0 to SLR-3.

  2. Right-click a Register Slice IP and select Block Properties and rename as axi_register_slice_3_s1.

  3. Double-click a Register Slice IP and set the Register Slice Option as Multi SLR Crossing as shown below.

    ../_images/vpk_multi_slr_crossing_3.png

  4. Open SLR Crossing tab, and set Number of SLR Crossing as 3 as shown below.

    ../_images/vpk_multi_slr_crossing_4.png

  5. Repeat step 39, step 40, and step 41 for the second instance of the AXI Register Slice IP and rename as axi_register_slice_3_s3.

  6. Disconnect axi_gpio_0 , axi_gpio_1 , axi_gpio_2 and axi_gpio_3 from AXI smart connect and connect the register slices as shown below.

    ../_images/vpk_register_slice_con.PNG

  7. Click Run Connection Automation in the Block Design view. Select aclk of all register slices and click OK.

    ../_images/vpk_register_slice_con_clk.png

  8. Double-click axi_uartlite_0 to open the IP. Go to the IP Configuration tab and configure the settings as shown in the following figure.

    ../_images/vpk_configure-ip-settings.png

  9. Add Clock Wizard IP. Double-click to open the IP.

  10. Go to Clocking Features tab and set the configuration as shown below:

    ../_images/clocking-features.png

  11. Make sure the Source option in Input Clock Information is set to Global buffer.

  12. Go to Output clocks tab and configure the output clock as 250 MHz as follows:

    ../_images/vpk_output-clocks-tab.png

  13. Right-click pl0_ref_clk of CIPS and click Disconnect Pin.

  14. Connect the pl0_ref_clk from CIPS to input clk_in1 of the Clocking wizard.

  15. Connect the output of clocking wizard to slowest_sync_clock of Processor System Reset IP.

    This helps in avoiding timing failure.

The overall block design is shown in the following figure:

../_images/vpk_image73.png