Configuring PL AXI GPIO and AXI UART - Configuring PL AXI GPIO and AXI UART - 2025.2 English - UG1305

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

Document ID
UG1305
Release Date
2025-12-09
Version
2025.2 English

This section describes the PS and PL configurations and the related connections to create a complete system with AXI GPIO and AXI UART. You can do this by adding the required IPs from the AMD Vivado™ IP catalog and then connect the components to blocks in the PS subsystem. To configure the hardware, follow these steps: