Configuring NoC and CIPS - Configuring NoC and CIPS - 2025.2 English - UG1305

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

Document ID
UG1305
Release Date
2025-12-09
Version
2025.2 English
  1. Open CIPS → PS-PMC.

  2. Click NoC and enable the NoC coherent, non-coherent interfaces and the NoC to PMC interfaces for Master SLR (SLR-0) as shown below.

    ../_images/vpk_noc-interface-slr0.png
  3. Enable PMC to NoC and NoC to PMC connectivity for slave SLRs (SLR-1, SLR-2, SLR3) as shown below.

    ../_images/vpk_noc-interface-slr-1.png ../_images/vpk_noc-interface-slr-2.png ../_images/vpk_noc-interface-slr-3.png
  4. Click OK and Finish to close the CIPS GUI.

  5. Add two AXI NoC IP from the IP catalog.

  6. Double-click the axi_noc-0. From Board tab, enable the LPDDR triplet and associated clocks as shown below.

    ../_images/vpk_noc_board.png
  7. Select the General tab, set Number of AXI Slave interfaces, AXI Clocks to 8, and the Number of Inter-NoC Master Interfaces to 5 as shown below.

    ../_images/vpk_noc-settings.png
  8. From the Inputs tab, configure the following settings for the eight AXI Slave interfaces as shown below.

    ../_images/noc-axi.png
  9. Configure the following settings from the Connectivity tab.

    ../_images/vpk_noc-connectivity.png
  10. Click OK.

  11. Double-click the axi_noc-1. From General tab, set Number of AXI Slave interfaces to 3, Number of AXI Master interfaces to 4, AXI Clocks to 7, and the Number of Inter-NoC Slave Interfaces to 5 as shown below.

../_images/vpk_noc_board1.png
  1. From the Inputs tab, configure the 3 AXI Slave interfaces to PS PMC as shown below:

../_images/vpk_noc-axi1.png
  1. From the Outputs tab, configure the 4 AXI Master interfaces to PS PMC as shown below:

../_images/vpk_noc-axi2.png
  1. Configure the following settings from the Connectivity tab.

../_images/vpk_noc-connectivity1.png
  1. Click OK.

  2. Make connections between CIPS and NoC as shown below.

../_images/vpk_noc-ip-new_view.png