Configuring Hardware - Configuring Hardware - 2025.2 English - UG1305

Versal Adaptive SoC Embedded Design Tutorial (UG1305)

Document ID
UG1305
Release Date
2025-12-09
Version
2025.2 English

The first step in this design is to configure the PS and PL sections. You can do this using the Vivado IP integrator. Start with adding the required IPs from the Vivado IP catalog and then connect the components to blocks in the PS subsystem. To configure the hardware, follow these steps:

Note

If the Vivado Design Suite is open already, jump to step 3.

  1. Open the Vivado project you created in Versal CIPS and NoC (DDR) IP Core Configuration.

    C:/edt/edt_versal/edt_versal.xpr

  2. In the Flow Navigator, under IP Integrator, click Open Block Design.

    ../_images/image5.png
  3. Right-click the block diagram and select Add IP.