Adding and Configuring IP Addresses - Adding and Configuring IP Addresses - 2025.2 English - UG1305

To add and configure IP addresses, follow these steps.

1. Right-click the block diagram and select Add IP from the IP catalog.

2. Search for AXI GPIO and double-click the AXI GPIO IP to add it to your design.

3. Add another instance of the AXI GPIO IP into the design.

4. Search for AXI Uartlite in the IP catalog and add it into the design.

5. Click Run Connection Automation in the Block Design view.

   

   The Run Connection Automation dialog box opens.

6. In the Run Connection Automation dialog box, select the All Automation check box.

   

   This checks the automation for all the ports of the AXI GPIO IP.

7. Click GPIO of axi_gpio_0 and set the Select Board Part Interface to Custom as shown below.

   

8. Click S_AXI of axi_gpio_0. Set the configurations as shown in the following figure:

   

9. Repeat previous step 7 and Step 8 for axi_gpio_1.

10. Click S_AXI of axi_uartlite_0. Set the configurations as shown in the following figure:

    

11. This configuration sets the following connections:

    • Connects the S_AXI of AXI_GPIO and AXI Uartlite to M_AXI_FPD of CIPS with SmartConnect as a bridge IP between CIPS and AXI GPIO IPs.

    • Enables the processor system reset IP.

    • Connects the pl0_ref_clk to the processor system reset, AXI GPIO, and the SmartConnect IP clocks.

    • Connects the reset of the SmartConnect and AXI GPIO to the peripheral_aresetn of the processor system reset IP.

12. Click UART of axi_uartlite_0. Set the configurations as shown in the following figure:

    

13. Click OK.

14. Click Run Connection Automation in the block design window and select the All Automation check box.

15. Click ext_reset_in and configure the setting as shown below.

    

    This connects the ext_reset_in of the processor system reset IP to the pl_resetn of the CIPS.

16. Click OK.

17. Disconnect the aresetn of SmartConnect IP from peripheral_aresetn of processor system reset IP.

18. Connect the aresetn of SmartConnect IP to interconnect_aresetn of processor system reset IP.

    

19. Double-click the axi_gpio_0 IP to open it.

20. Go to the IP Configuration tab and configure the settings as shown in the following figure.

    

21. Make the same setting for axi_gpio_1.

22. Add four more instances of Slice IP.

23. Delete the external pins of the AXI GPIO IP and expand the interfaces.

24. Connect the output pin gpio_io_0 of axi_gpio_0 to slice 0 and slice 1.

25. Similarly, connect the output pin gpio_io_0 of axi_gpio_1 to slice 2 and slice 3.

26. Make the output of Slice IP as External.

27. Configure each Slice IP as shown below.

    

28. Double-click axi_uartlite_0 to open the IP.

29. In the Board tab, set Board interface as shown below:

    

30. Go to the IP Configuration tab and configure the settings as shown in the following figure.

    

31. Add Clock Wizard IP. Double-click to open the IP.

32. Go to Clocking Features tab and set the configuration as shown below:

    

33. Make sure the Source option in Input Clock Information is set to Global buffer.

34. Go to Output clocks tab and configure as follows:

    

35. Right-click pl0_ref_clk of CIPS and click Disconnect Pin.

36. Connect the pl0_ref_clk from CIPS to input clk_in1 of the Clocking wizard.

37. Connect the output of clocking wizard to slowest_sync_clock of Processor System Reset IP.

    This will help in avoiding timing failure.

The overall block design is shown in the following figure: