Versal Adaptive SoC Embedded Design Tutorial (UG1305) - 2025.2 English - Use the AMD Vivado™ Design Suite flow for a VCK190/VMK180/VPK180 evaluation board. - UG1305
Document ID
UG1305
Release Date
2025-12-09
Version
2025.2 English
Versal Adaptive SoC Embedded Design Tutorial (UG1305)
Getting Started
Navigating Content by Design Process
Hardware Requirements
Installation Requirements
Vitis Integrated Design Environment (IDE) and Vivado Design Suite
PetaLinux Tools
Prerequisites
Extracting the PetaLinux Package
Software Licensing
Tutorial Design Files
Versal ACAP CIPS and NoC (DDR) IP Core Configuration
Prerequisites
CIPS IP Core Configuration
Creating a New Embedded Project with a Versal Device
Starting Your Design
Creating an Embedded Processor Project
Managing the Versal CIPS IP Core in the Vivado Design Suite
Validating the Design and Generating the Output
Synthesizing, Implementing, and Generating the Device Image
Exporting Hardware
Running a Bare-Metal Hello World Application
Creating a Hello World Application for the Arm Cortex-A72 on OCM
Creating the Platform
Creating a Hello World Application from Example
Modifying the helloworld_a72 Application Source Code
Building the Application
Creating the Standalone Application Project for the Arm Cortex-R5F
Modifying the helloworld_r5 Application Source Code
Building the Application
Modifying the Application Linker Script for the Application Project helloworld_r5
Running Applications in the JTAG Mode using the System Debugger in the Vitis Software Platform
Creating a Run Configuration for the System Project
Creating a Run Configuration for a Single Application within a System Project
Method I
Method II
NoC (and DDR) IP Core Configuration
Configuring the NoC IP Core in an Existing Project
Configuring Your Design
Validating the Design and Generating the Output
Synthesizing, Implementing, and Generating the Device Image
Exporting Hardware
Running a Bare-Metal Hello World Application on DDR Memory
Boot and Configuration
System Software
Platform Loader and Manager
U-Boot
Trusted Firmware-A
Generating Boot Image for Standalone Application
Loading PetaLinux Images on a Versal Board using JTAG
Boot Sequence for SD-Boot Mode
Boot Sequence for QSPI Boot Mode
Debugging Using the Vitis Software Platform
Customized System Debugger
Debugging Software Using the Vitis Software Platform
Connecting with the Target
Debugging Using the Software Command Line Tool (XSCT)
Setting Up a Target
Loading the Application Using XSCT
Configuring the Serial Terminal
Running and Debugging Application Using XSCT
System Design Example using Scalar Engine and Adaptable Engine
Design Example: Using AXI GPIO
Configuring Hardware
Connecting IP Blocks to Create a Complete System
Adding and Configuring IP Addresses
Validating the Design and Generating the Output
Synthesizing, Implementing, and Generating the Device Image
Exporting Hardware
Example Project: FreeRTOS AXI UARTLITE Application Project with RPU
Creating the Platform
Creating an Empty Application
Building the Application
Example Project: Creating Linux Images Using PetaLinux
Combining FreeRTOS and APU Images using a BIF File
System Design Example for High-Speed Debug Port (HSDP) with SmartLynq+ Module
Introduction
Design Example: Enabling the HSDP
Modifying the Design to Enable the HSDP
Synthesizing, Implementing, and Generating the Device Image
Exporting Hardware (XSA)
Creating the HSDP-enabled Linux Image Using PetaLinux
Setting Up the SmartLynq+ Module
Using the SmartLynq+ as a Serial Terminal
Booting Linux Images over JTAG or HSDP
Useful Links
Summary
System Design Example for SSI Devices
Design Example: Using AXI GPIO
Versal CIPS IP Core Configuration
Managing the Versal CIPS IP Core in the Vivado Design Suite
NoC (and DDR) IP Core Configuration
Configuring NoC and CIPS
Configuring PL AXI GPIO and AXI UART
Configuring CIPS PS-PL interface
Configuring PL Hardware
Validating the Design and Generating the Output
Synthesizing, Implementing, and Generating the Device Image
Exporting Hardware
Example Project: FreeRTOS AXI UARTLITE Application Project with RPU
Creating the Platform
Creating an Empty Application
Building the Application
Example Project: Creating Linux Images Using PetaLinux
Appendix: Creating the PLM
Creating the Platform
Creating a Versal PLM Application from Example