The XPm_DevIoctl EEMI API allows a
platform management master to perform specific operations to certain devices.
RPU NODE IDs for Versal devices are as follows:
- PM_DEV_RPU0_0
- PM_DEV_RPU0_1
RPU NODE IDs for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices are as follows:
- PM_DEV_RPU_A_0
- PM_DEV_RPU_A_1
- PM_DEV_RPU_B_0
- PM_DEV_RPU_B_1
- PM_DEV_RPU_C_1
- PM_DEV_RPU_D_0
- PM_DEV_RPU_D_1
- PM_DEV_RPU_E_0
- PM_DEV_RPU_E_1
- PM_DEV_RPU_C_0
The following table lists the supported operations in Versal devices.
| ID | Name | Description | Arguments | ||||
|---|---|---|---|---|---|---|---|
| Node ID | Arg1 | Arg2 | Arg3 | Return Value | |||
| 0 | IOCTL_GET_RPU_OPER_MODE | Returns current RPU operating mode | RPU NODE ID | - | - | - | Operating mode: 0: LOCKSTEP 1: SPLIT |
| 1 | IOCTL_SET_RPU_OPER_MODE | Configures RPU operating mode | RPU NODE ID | Value of operating mode 0: LOCKSTEP 1: SPLIT |
- | - | - |
| 2 | IOCTL_RPU_BOOT_ADDR_CONFIG | Configures RPU boot address |
RPU NODE ID |
Value to set for boot address 0: LOVEC/TCM 1: HIVEC/OCM |
- | - | - |
| 3 | IOCTL_TCM_COMB_CONFIG | Configures TCM to be in split mode or combined
mode Note: This is not
applicable for Versal AI Edge Series Gen 2
and Versal Prime Series Gen 2
devices.
|
NODE_RPU_0 NODE_RPU_1 |
Value to set (Split/Combined) 0: SPLIT 1: COMB |
- | - | - |
| 4 | IOCTL_SET_TAPDELAY_BYPASS | Enable/disable tap delay bypass | NODE_QSPI | Type of tap delay 2: QSPI |
Tapdelay Enable/Disable 0: DISABLE 1: ENABLE |
- | - |
| 6 | IOCTL_SD_DLL_RESET | Resets DLL logic for the SD device | NODE_SD_0, NODE_SD_1 |
SD DLL Reset type 0: ASSERT 1: RELEASE 2: PULSE |
- | - | - |
| 7 | IOCTL_SET_SD_TAPDELAY | Sets input/output tap delay for the SD device |
NODE_SD_0, NODE_SD_1 |
Type of tap delay to set 0: INPUT 1: OUTPUT |
Value to set for the tap delay | - | - |
| 12 | IOCTL_WRITE_GGS (Global General Storage) | Writes value to GGS register | - | GGS register index (0/1/2/3) | Register value to be written | - | - |
| 13 | IOCTL_READ_GGS (Global General Storage) | Returns GGS register value | - | GGS register index (0/1/2/3) | - | - | Register value |
| 14 | IOCTL_WRITE_PGGS (Persistent Global General Storage) | Writes value to PGGS register | - | PGGS register index (0/1/2/3) | Register value to be written | - | - |
| 15 | IOCTL_READ_PGGS (Persistent Global General Storage) | Returns PGGS register value | - | PGGS register index (0/1/2/3) | - | - | Register value |
| 17 | IOCTL_SET_BOOT_HEALTH_STATUS | Sets healthy bit value to indicate boot health status to firmware | - | healthy bit value | - | - | - |
| 21 | IOCTL_OSPI_MUX_SELECT | Select OSPI AXI Multiplexer | NODE_OSPI | Operation mode 0: Select DMA 1: Select Linear 2: Get mode |
- | - | Get mode 0: DMA 1: Linear |
| 22 | IOCTL_USB_SET_STATE | Set USB controller in different device power states | NODE_USB_0 | Requested power state 0: D0 1: D1 2: D2 3: D3 |
- | - | - |
| 23 | IOCTL_GET_LAST_RESET_REASON | Get last reset reason of system | - | - | - | - |
0 – The POR button was pressed outside of the system 1 – An internal POR was caused by software 2 - One of the other SSIT slices caused a POR 3 - An error caused a POR 7 - JTAG TAP initiated system reset 8 - Error initiated system reset 9 - Software initiated system reset 10 - One of the other SSIT slices caused a system reset 15 – Invalid reset reason |
| 24 | IOCTL_AIE_ISR_CLEAR | Clear AI Engine NPI Interrupts Note: This feature is currently not supported for
Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2
devices.
|
DEV_AIE (0x18224072U) | 4-bit NPI Interrupt Clear Mask (wtc) Bit<3-0> correspond to Interrupt<3-0> |
- | - | - |
| 28 |
IOCTL_READ_REG |
Used to securely read a given offset address for a given node ID. | - | Offset | count (=1) | - | - |
| 29 | IOCTL_MASK_WRITE_REG | Used to securely write to a given offset address for a given node ID. | - | Offset | mask | Value | - |
| 33 | IOCTL_AIE_OPS | AIEML/AIE1 runtime operations for partition init and tear-down. | DEV_AIE or Partition node ID (currently unused). | Arg1(15:0): Start column of partition for which
wants to run the operation. Arg1(31:16): Number of columns in partition (or End Column of partition) |
Red value of operation. Here, each bit is
related to one operation as below: Bit value 1 indicate that the operation need to be perform. |
- | XST_SUCCESS or Error Code. |
| 39 | IOCTL_AIE2PS_OPS | AIE2PS runtime operations | No change | AIE2PS Ops Buffer Size | Higher 32 bits of the buffer physical address | Lower 32 bits of the buffer physical addres | |
| 34 | IOCTL_GET_QOS | Get device QoS value Note: This feature is currently not supported for
Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2
devices.
|
- | - | - | - | Response returns two values: 0: Default QoS value 1: Current QoS value |
| 35 | IOCTL_GET_APU_OPER_MODE | Return the current APU operating mode Note: This feature is only
supported for Versal AI Edge Series Gen 2
and Versal Prime Series Gen 2
devices.
|
APU node ID for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices | - | - | - | Operating mode: 0: SPLIT 1: LOCKSTEP |
| 36 | IOCTL_SET_APU_OPER_MODE | Configures APU operating mode Note: This feature is only
supported for Versal AI Edge Series Gen 2
and Versal Prime Series Gen 2
devices.
|
APU node ID for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices | Value of operating mode: 0: SPLIT 1: LOCKSTEP |
- | - | - |
| 37 | IOCTL_PREPARE_DDR_SHUTDOWN 1 | Prepare LPDDR SDRAM device for shutdown | PM_DEV_DDR_0 | - | - | - | XST_SUCCESS or XPM_INVALID_DEVICE_ID or XPM_ERR_DEVICE_STATUS or Other Error Code |
| 38 | IOCTL_GET_SSIT_TEMP | Sysmon node ID + SLR number Note: This feature is
currently not supported for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices.
|
Local sysmon min/max temperature register offset | - | - | - | SSIT temperature data |
|
|||||||
Note: IOCTL_GET_QOS currently only
supports AI Engine partition nodes for AI Engine clock frequency. The default QoS represents
the original boot time divider value and the current QoS value represents the
current divider value that is set.
| 31st to 10th | 9th | 8th | 7th | 6th | 5th | 4th | 3rd | 2nd | 1st | 0th |
|---|---|---|---|---|---|---|---|---|---|---|
| Reserved | Zeroization of Memtile (Supported for AI Engine2 only) | Zeroization of data memory | Zeroization of program memory | Set L2 controller NPI INTR | Enable AXI4 error events | Disable column clock buffer | Zeroization of program and data memories | Enable column clock buffer | Shim reset | Column reset |
| Operation | Value |
|---|---|
| Coumn reset | 1 |
| Shim Reset | 2 |
| UC Zeroization | 3 |
| Enable Column Clock buffer | 4 |
| Handshake operation | 5 |
| Clear hardware error status | 6 |
| Number of coulmns start | 7 |
| Data & Program memory zeroization | 8 |
| AXIMM isolation | 9 |
| NMU config | 10 |
| Disable privillage memory | 11 |
| Disable memory interleave | 12 |
| Pause UC DMA transaction | 13 |
| Pause NOC DMA transaction | 14 |
| Set ECC scrub period | 15 |
| Disable column clock buffer | 16 |
| Configure hardware errors interrupt | 17 |
| Mask hardware error interrupts | 18 |
| Enable privileged memory | 19 |
| Eanble AXI-MM error event | 32 |
| Set L2 controller NPI interrupt | 64 |
| Program memory zeroization | 128 |
| Data memory zeroization | 256 |
| Mem time zeroization | 512 |