The RPU provides improved performance at an improved safety level. However, for real-time applications which require a higher level of safety (for example, ASIL-C/SIL3), reliability, and determinism, real-time processing unit (RPU) is used with a Cortex-R52 processor subsystem.
The RPU consists of up to ten Arm Cortex-R52 processor cores with lock-step option, based on the Armv8-R architecture.
- The dual cores can operate as two Dual-Core Lock-Step (DCLS) processing units with each core being the redundant copy of another one and inclusion of the necessary redundant comparators.
- 128 KB TCM per Cortex-R52 processor in split mode.
- Option to combine 128 KB of TCM in lock-step mode.
- 2 MB of on-chip memory with error correction code (ECC) accessible by both the RPU and the APU.
- 32 KB L1 instruction cache with error correction code (ECC) or parity and 32 KB L1 data cache with error correction code (ECC)
- Generic interrupt controller (GIC) to support GIC architecture
- Power-gating support per split core
- TrustZone aware