Phase 3: Boot and Configuration Sequence by PLM - 2025.2 English - UG1304

Versal Adaptive SoC System Software Developers Guide (UG1304)
Document ID
UG1304
Release Date
2025-12-08
Version
2025.2 English
Figure 1. Phase 3: Load Platform
9
The PPU begins to execute the PLM from the PPU RAM.
10
The PLM reads and processes the PDI components.
11
The PLM configures other parts of the Versal device using the PDI contents.
11a
The PLM applies the configuration data to the following components:
  • PMC, PS blocks (CDO files)
    • Multiplexed I/Os (MIOs), clocks, resets, and etc.
  • NoC initialization and NPI components (NPI file)
    • DDR memory controller, NoC for initial Boot paths
    • The PLM loads the applications and data for the APU and RPU processors to various memories specified by the ELF file. These memories include on-board DDR memory and internal memories, such as OCM and TCM.
      Note: The PMC triggers the scan clear of the individual programming control/status registers.
11b
Load APU/RPU software
11c
PL Logic Configuration. (this will be part of PLD.PDI. See note below)
  • PL data (CFI file)
  • NoC Configuration data (NPI file) for PL to NoC, GTs, XPIPE, I/Os, clocking, etc.
  • AI Engine configuration (AI Engine CDO)
Note:
  1. Segmented Configuration is standard design flow for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2, resulting into generation of Boot.PDI and PLD.PDI. This allows flexibility to load PLD.PDI later. For more information, refer to Segmented Configurationsection.
  2. You can also have the PLD.PDI loaded during boot sequence by merging Boot.PDI and PLD.PDI using BIFs or using PLM Secondary boot option (refer to boot_device attribute in Bootgen User Guide (UG1283)).