The system boot is managed by the platform management controller (PMC). The ROM code unit (RCU) boots the hardware and loads the initial platform loader and manager (PLM) firmware into the PPU processor.
Boot Sequences and Platform Control Functions are described in Platform Boot, Control, and Status section in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).
The integrated hardware is configured with programmable device image (PDI) files. The PDIs are composed of images and configuration data object (CDO) files that are loaded or processed by the PLM. This includes configuring the PS, NoC, DDR memory controller, and others.
The PMC operations are divided into four phases beginning with a hardware reset that starts or restarts the RCU executing its BootROM code. After reset, the RCU configures the system to access the boot device to find and process the boot header. The RCU downloads the PLM firmware from the boot device and writes it into the PPU processor memory.
When the RCU finishes with the device boot, the PLM takes control of the system for further configuration and to load system software for the RPU, APU, and processors in the programmable logic. The PLM loads the application security unit (ASU) firmware.
The phases are:
- Pre-boot (phase 1): power-up and reset (PMC hardware)
- Boot setup (phase 2): initialization and boot header processing (RCU BootROM code)
- Load platform (phase 3): boot image processing and device configuration (PPU PLM firmware)
- Post-boot (phase 4): platform management and monitoring services (RCU and PLM)
During normal runtime, the PLM firmware monitors and responds to system requests and events. The PMC is in all devices and is required for all operating modes.
- Hardware reset control circuits and sequencers
- Initialization of the device after a power-on reset (POR) and system reset (SRST) by the RCU BootROM
- Boot and configuration from a supported boot device
- Configure the adaptable engines in the PL using the configuration frame interface (CFI)
- Performs security core functions that supports encryption and decryption, authentication, and key management
- Provides test and debug infrastructure to support boundary-scan and Arm® CoreSight™ trace and debug
- Monitors system activity and responds to security and functional safety events
- Releases the PSXC from reset
- Controls system power
- Manages system errors.
For more information, refer to PMC Subsystem Section in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).