PMC Memory Layout - 2025.1 English - UG1304

Versal Adaptive SoC System Software Developers Guide (Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2) (UG1304)

Document ID
UG1304
Release Date
2025-06-23
Version
2025.1 English

This section contains the approximate details of the PMC memory layout and the PLM memory footprint, with the various PLM build options.

The following figure shows the PMC memory layout.

Figure 1. PMC Memory Layout

Note: For Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices, the PPU RAM size is 640 KB. 384 KB is the PPU RAM size for Versal devices.

In the PLM, the PLM_DEBUG and PLM_PRINT_PERF build flags along with all modules, are enabled by default.