PLM Boot and Configuration - 2025.2 English - UG1304

Versal Adaptive SoC System Software Developers Guide (UG1304)

Document ID: UG1304
Release Date: 2025-12-08
Version: 2025.2 English

Overview
Introduction to Versal Adaptive SoCs
Navigating Content by Design Process
About This Guide
Programming View
Versal Devices
Hardware Overview
Key Hardware Components
Components Available in Versal Devices
Processing System
Application Processing Unit
Real-Time Processing Unit
Tightly Coupled Memory Interface
RPU Configuration Options
Programmable Logic
MicroBlaze Processors in the Programmable Logic
Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 Devices
Hardware Overview
Key Hardware Components
Processing System
APU Subsystem
RPU Subsystem
Tightly Coupled Memory Interface
PMC Subsystem
ASU Subsystem
Programmable Logic
PL Configuration
NoC Interconnect
DDR Memory Controller
DDR5 Enhanced Memory Controller
Development Tools
Vivado Design Suite
Vitis Software Platform
Accelerated Flow
Embedded Flow for Versal Devices
Embedded Development Framework for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 Devices
Vitis Tools
System Device Tree Flow
Open Source
AMD GNU Tools
Linux Software Development Using Yocto
Yocto Project Development Environment
Software Hardware Exchange Loop Flow
QEMU
QEMU Model for Versal Devices
QEMU Model for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 Devices
AI Engine
AI Engine Development Environment for Versal Devices
AI Engine Software Development Flow
AI Engine Runtime Stack
AI Engine Development Environment for Versal AI Edge Series Gen 2 Device
Software Stack
Bare-Metal Software Stack
The C Standard Library (libc)
The C Standard Library Mathematical Functions (libm)
Standalone BSP
Versal Devices
Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 Devices
Linux Software Stack
FreeRTOS Software Stack for Versal Devices
Third-Party Software Stack
Software Development Flow for Versal Devices
Bare-Metal Application Development in the Vitis Environment
Linux Application Development Using the Vitis Software Platform
Software Design Paradigms
Frameworks for Multiprocessor Development
Symmetric Multiprocessing
Symmetric Multiprocessing for Versal Devices
Symmetric Multiprocessing for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 Devices
Execution Domain and Images
Asymmetric Multiprocessing
OpenAMP
Virtualization with Hypervisor
Use of Hypervisors
Boot and Configuration
Boot Process
Phase 1: Pre-Boot
Phase 2: Boot Setup
Phase 3: Boot and Configuration Sequence by PLM
Phase 4: Loading other PDIs (Secondary Boot, PLD.PDI)
Boot Flow
Secure Boot Flow
Segmented Configuration
Boot Device Modes
Secondary Boot Process and Device Choices
Boot Process for Primary Boot Device
Fallback Boot and MultiBoot
Boot Mode Search Limits
Octal-SPI and Quad-SPI Boot Devices
SD/eMMC Boot Devices
SD/eMMC RAW Boot Mode
Programmable Device Image
Configuration Data Object
Creating a Boot Image (PDI)
Software Developer Control of PDI File Creation via BIF File
Methods for Programming the PDI to a Primary Boot Device
Platform Loader and Manager
PLM Boot and Configuration
BootROM, PLM Handoff State
PLM Subsystem
LPD Configuration
PL Configuration
FPD Configuration
DFX Configuration
CPM Configuration
Processor Subsystem Configuration
AI Engine Configuration
PLM Software Details
PLM Responsibilities
PLM Architecture
PLM Software
PLM Execution Flow
Versal Devices Using SSI Technology
Boot Flow for SSI Devices
SLR PDIs
CDO Commands for Devices Using SSI Technology
SSI Technology Sync Slaves
SSI Technology Sync Master
SSI Technology Wait Slaves
PLM-to-PLM Communication in SSI Devices
High-level APIs in PLM
Initialize Events
Register Events
Write Event Buffer and Trigger Message Event
Trigger Event
Wait for Event
Read Event Response
Write Event Response and Ack the Message Event
Send Message Event and Get Response
Acknowledge Event
Send Message Event and Get Response
SSI Technology Interrupt Handlers
SSI Technology Message Event Handler
Example Flow
Supported Events
Reading Device Temperature on SSI Devices
Secure PLM-to-PLM Communication on SSI devices
Description
Key-IV Change at Boot Time
Communication at Runtime
Key-IV change at runtime
Protocols
RTCA Locations Reserved
Implementation Details
Existing Implementation
Example Flow
For Key-IV Establishment at Boot Time
For Communication at Runtime
For Key-IV change at Runtime
PLM Errors
PLM Major Error Codes
Exception Handling
PLM Event Logging
Logging PLM Terminal Prints
Logging Trace Events
Event Logging IPI Command
Event Logging Command Examples
Glitch Detection
Error Manager
Error Management Hardware
Error Management API Calls
Error Management CDO Commands
Set EM Action
Register Notifier for EM Events
Notify Callback
Error Events
PLM Interface (XilPLMI)
PLM Secure Lockdown Flow
Secure Lockdown Support in PLM
Secure Lockdown Sequence
SSI Devices Secure Lockdown
AES/SHA Events Queuing Mechanism
XilLoader
Image Store
XilLoader/IPI CDO Commands
Load Partial PDI
Load DDR Copy Image
Update MultiBoot
Upgrade ImageStore
Deferred Image Loading
Selective CFrame Readback
XilPM
XilSecure
XilSEM
PLM Usage
PLM Build Flags
PMC Memory Layout
Services Flow
Security
Security Features
Secure Boot
Checksum Verification
Asymmetric Hardware Root-of-Trust (A-HWRoT) (Authentication Required)
RSA Engine
Elliptic Curve Cryptography Engine
Key Revocation
Encryption
DPA Counter Measures
Key Sources
Red Key
Black Key
User Key
Revocation
Symmetric Hardware Root-of-Trust (S-HWRoT) Boot Mode (Encryption Required)
True Random Number Generator
Application Security Unit Firmware
Platform Management
Overview
Power Domains
Dynamic Voltage Scaling for -2LI Graded Parts
Controlling the Versal Power Domain Using GPIO
DFX Management for Versal Devices
Platform Management Software Architecture
API Calls and Responses
Platform Management Communication Using IPIs
Platform Management Layers
Typical Platform Management API Call Flow
Requesting and Releasing Peripheral Nodes
Platform Management Default Subsystem
ASU Subsystem
Activation of Subsystem
Using the API for Power Management
Implementing Power Management on a Processor Unit
Initializing the XilPM Library
Power Management Using XPm_InitFinalize
Working with Memory and Peripheral Devices
Requesting and Releasing a Node
Setting up Device Request Permissions
Requesting and Releasing a Device From a Standalone Application
AI Engine Clock Frequency Scaling
Changing Requirements
Self-Suspending
Setting a Wake-up Source
Resuming Execution
Suspend-Resume Flow
Suspending the Entire FPD Domain
Forcefully Powering Down the FPD
Using API for Warm Restart and Subsystem Restart Management
Warm Restart
Subsystem Restart
Subsystem Restart Request from Other Subsystems
Linux Self-Subsystem Restart Sequence from Linux
Healthy Boot Monitoring
Subsystem Restart When Linux is Hang
Using the API for Reset Management
Using the API for Pin Management
Using Miscellaneous APIs
XPm_DevIoctl EEMI API
XPm_GetOpCharacteristic EEMI API
XPm_Query EEMI API
XPm_ActivateSubsystem API
Versal Secure Register Access with IOCTL
Using the API for Clock Management
Event Management Framework
Event Management in Standalone Application
Registering and Unregistering the Event Handler
Event Management in Linux Kernel
Registering and Unregistering the Event Handler
XilPM Client Implementation Details
Payload Mapping for API Calls to PMC
Payload Mapping for API Callbacks from the PMC
Issuing EEMI API Calls to the PMC
Handling API Callbacks from the PMC
PM Features in Linux
User Space Platform Management Interface
System Power States
Power Management for the CPU
CPU Hot-Plugging
CPU Idle
CPU Frequencies
Power Management for the Devices
Clock Gating
Runtime Power Management
Global General Storage Registers
Persistent Global General Storage Registers
Debug Interface
PM Linux Drivers
Trusted Firmware-A
Event Handling in TF-A
TF-A Application Binary Interface
Checking the API Version
Checking the Chip ID
Power State Coordination Interface
PS Management Controller Firmware
Relationship with PLM
General Flow of an EEMI API Call
Runtime Decoupling Using Version Control of the EEMI API
PSM Health Check in PLM
Deprecation of Request Suspend API
Deprecation of Processor and Power Domain Support in Force Power Down API
Target Development Platforms
Boards and Kits
Libraries
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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