The connections and configuration of the PL elements are captured in the AMD Vivado™ Design Suite and the AMD Vitis™ unified software platform tool chain using a programmable device image (PDI). The PDI contains PL configuration frames (CFRAME), which are sent by the PLM to the configuration frame unit (CFU) for processing. The CFU interfaces to the PL via the configuration frame interface (CFI). The PL can be configured during the boot process and can be reconfigured during normal system operation. The PL configuration can be read-back for debug and functional safety applications. The CFU is described in Configuration Frame Unit and the CFI is described in Configuration Frame Interface.
For more information, refer to Hardware Architecture PL section in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026)