Key Hardware Components - 2024.1 English

Versal Adaptive SoC System Software Developers Guide (UG1304)
Document ID
UG1304
Release Date
2024-05-30
Version
2024.1 English

The following list describes the largest hardware components.

APU
See Components Available in Versal Devices.
AXI Interconnect
The advanced eXtensible interface (AXI) interconnect connects one or more memory mapped AXI master devices to one or more memory mapped peripheral devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from Arm, including the AXI4-Lite control register interface subset.
CPM
See Components Available in Versal Devices.
PL
The programmable logic (PL) is a scalable structure that includes adaptable engines and intelligent engines that can be used to construct accelerators, processors, or almost any other complex functionality. It is configured using the AMD Vivado™ tools. The architect determines the components to be available in the PL design. For example, the MicroBlaze processor is an IP core, so you can optionally add MicroBlaze processors to the design. For more information on the PL, see the MicroBlaze Processor Reference Guide (UG984).
PMC
The platform management controller (PMC) handles device management control functions such as device reset sequencing, initialization, boot, configuration, security, power management, dynamic function eXchange (DFX), health-monitoring, and error management. You can boot the device in either secure or non-secure mode.

For more information on PMC in Versal devices, refer to the Platform Management Controller section in Versal Adaptive SoC Technical Reference Manual (AM011).

NoC Interconnect
See Components Available in Versal Devices.
RPU
See Components Available in Versal Devices.
System Memory Management Unit
The system memory management unit (SMMU) supports memory virtualization for peripherals. The main functions of the SMMU include logical memory protection by performing address translation, transaction security state control, as well as blocking peripherals if configured to do so.

These functions are performed with a combination of the seven translation buffer units (TBU 0 to 6). In Versal devices, four of these are in the path of incoming AXI interfaces outside of the FPD to the cache coherent interconnect (CCI). The translation and protection tables that are cached in the TBU are updated by the SMMU translation control unit (TCU).

For more information on FPD SMMU in Versal devices, see Chapter 43 in the Versal Adaptive SoC Technical Reference Manual (AM011).

Cache Coherent Interconnect (CCI)
See Components Available in Versal Devices.

Additional Hardware Components

Peripheral Controllers
The Input/Output peripherals are present in low power domain (LPD) and PMC domain (PPD). The flash memory controllers (FMC) are located in PMC. Their I/O signals are routed to device pins via the PMC MIO multiplexer.

For more information on peripherals in Versal devices, refer to the I/O Peripherals and Flash Memory Controllers sections in Versal Adaptive SoC Technical Reference Manual (AM011).

Interconnects and Buses
Versal adaptive SoCs has following additional interconnects and buses:
NPI
The NoC programming interface, a 32-bit programming interface to the NoC and several attached units.

For more information, refer to Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

APB
The advanced peripheral bus (APB) is a 32-bit single-word read/write programming interface. This bus is used to access control registers in the functional units, i.e., subsystem units. These control registers are used to program the functional units. The APB switch is used as the interconnect switch in the following four areas:
  • PMC
  • LPD
  • FPD
  • CPM
CFI
The configuration frame interface (CFI) transports PL and integrated hardware configuration information contained in the boot image from the PMC to its destination within the Versal device. CFI provides a dedicated high-bandwidth 128-bit bus to PL for configuration and readback.

For more information on CFI in the Versal adaptive SoCs, refer to the Programming Interfaces chapter in Versal Adaptive SoC Technical Reference Manual (AM011).

System Watchdog Timer
The system watchdog (SWDT) timer is used to detect and recover from various malfunctions. The watchdog timer can be used to prevent system lockup (when the software becomes trapped in a deadlock).

For more information on System Watchdog Timer in Versal devices, refer to System Watchdog Timer section in Versal Adaptive SoC Technical Reference Manual (AM011).

Clocks
Versal devices have the following clocks:
  • PMC and PS clocks
  • CPM clocks
  • NoC, AI Engine, and DDR memory controller clocks
  • PL clocks: The PL includes its own clock arrays that are programmed when blocks are instantiated. The PL also includes programmable clock modules that can be driven by clocks from input pins and other sources.

For more information, see the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003) and Versal Adaptive SoC Technical Reference Manual (AM011).

Memory
Versal devices have following types of memories:
DDR memory
Up to 4096 GB of RAM is supported. This DDR memory is external to the device.
On-chip memory (OCM)
See Components Available in Versal Devices.
Accelerator RAM
The 4 MB accelerator RAM (XRAM) is available in some Versal AI Core series. The XRAM is divided into four separate memory banks with four system interfaces: an AXI port from the LPD PS and three PL AXI ports.

The XRAM supports simultaneous access by each port to its associated bank. It also allows full cross-bank access from any port to any bank.

For details of XRAM in Versal devices, refer to XRAM Memory chapter in the Versal Adaptive SoC Technical Reference Manual (AM011).

Tightly coupled memory (TCM) in the RPU
See Components Available in Versal Devices.
Battery-backed RAM (BBRAM)
This memory can store the advanced encryption standard (AES) 256-bit key.
eFUSE
Contains user memory to store multiple keys and security configuration settings.
Reset
Versal devices have several layers of resets with overlapping effects. The highest-level resets are generally aligned with power domains, followed by power island resets, and finally individual functional unit resets. In some cases, functional units have local resets that affects part of the block. The reset hierarchy is as follows:
  • Subsystem resets (power domains)
  • Power-island resets
  • Functional unit (block) resets
  • Partial resets of a block (some cases)

For more information on Resets in Versal devices, refer to the Resets chapter in Versal Adaptive SoC Technical Reference Manual (AM011).

Virtualization
The Versal device includes the following hardware components for virtualization:
  • CPU virtualization
  • Memory virtualization

For more information on Virtualization in Versal devices, refer to Shared Virtual Memory section in Versal Adaptive SoC Technical Reference Manual (AM011).

Security and Safety
The Versal device has the following security management and safety features:
  • Secure key storage and management
  • Tamper monitoring and response
  • User access to AMD hardware cryptographic accelerators
  • Xilinx memory protection unit (XMPU) and Xilinx peripheral protection unit (XPPU) provides hardware-enforced isolation.
  • TrustZone

For more information, refer to Platform Management Controller in Versal Adaptive SoC Technical Reference Manual (AM011), Security, and Versal Adaptive SoC Security Manual (UG1508). This manual requires an active NDA to download from the Design Security Lounge.

For XMPU and XPPU in Versal devices, refer to Memory Protection in Versal Adaptive SoC Technical Reference Manual (AM011).