Glitch Detection - 2024.2 English - UG1304

Versal Adaptive SoC System Software Developers Guide (UG1304)

Document ID
UG1304
Release Date
2024-12-13
Version
2024.2 English

PLMI client supports the required APIs to configure and handle glitch detectors in versal. The provision is given to user to update, configure, enable/disable and check status of glitch detectors in both secure(/client) and non-secure(/server) mode. To enable secure mode, XPLMI_GLITCHDETECTOR_SECURE_MODE macro must be defined. Glitch detector 0/1 can be configured with desired depth, width and reference voltage.

Enabling of an interrupt and its service routine is provided with basic functionality in example. User code can be written in the provided service routine to perform required action on glitch detection. Refer to the following example:

embeddedsw/xplmi_glitch_detector_example.c at master ยท embeddedsw/embeddedsw

In secure mode, to access registers corresponding to glitch detector PM IP integrator commands are used. Glitch detection overlay CDO must be used to gain access to PMC_ANALOG registers and markers must be provided in the PMC CDO. Glitch detection overlay CDO is as follows:

marker 0x64 "SUBSYSTEM_DEFINITION/USERDEF/REG_ACCESS"
# node PMC_ANALOG_NODEID powerDomain power_pmc 0xf1160000 pmc_analog
pm_add_node 0x30100002 0xf1160000 0x4208001
# For PMC_ANALOG, size {0x1: 1 words} access {0x2: all read-write}
pm_set_node_access 0x30100002 0x1000000 0x2
marker 0x65 "SUBSYSTEM_DEFINITION/USERDEF/REG_ACCESS"

Direct register access is done in a non-secure mode.