Each SoC device can have multiple DDR5 memory controllers (DDRMC5). The number of memory controllers in a device is specified in the Versal Architecture and Product Data Sheet: Overview (DS950).
The SoC device includes one or more LP/DDR5 enhanced memory controllers (DDRMC5E) to provide high efficiency and low latency support for the PS processors and traditional FPGA applications like video, network buffering, etc.
Full-memory encryption is supported with AES-GCM and AES-XTS.
A built-in hardware masking feature is available when using AES-GCM or AES-XTS encryption to provide resistance to DPA or SCA. The DDRMC5E controller also includes these features:
- Higher bandwidth
- FUSA requirements and features
- Enhanced calibration features
For more information, refer to Hardware Architecture NoC Subsystem section in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).