Boot Device Modes - 2025.1 English - UG1304

Versal Adaptive SoC System Software Developers Guide (Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2) (UG1304)

Document ID
UG1304
Release Date
2025-06-23
Version
2025.1 English

The following tables show the boot device choices for primary boot, and the boot device modes.

Versal Devices

Note: This section is not applicable for Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices.

For additional information, see the Versal Adaptive SoC Technical Reference Manual (AM011).

Table 1. Primary Boot Device Modes for Versal Devices
Boot Mode Mode[3.0] Pin Setting Data Bus Width Secure Boot Fallback Boot and MultiBoot Search Offset Limit 3
eMMC1 (4.51) 0110 x1, x4, x8 yes yes

8191 (for FAT files)

Size of eMMC device (for raw boot mode)

JTAG 4 0000 x1 no no N/A
Octal SPI single or dual-stacked 5 1000 x8 yes yes 8 Gb
Quad SPI24 single or dual-stacked 5 0001 x1, x2, x4 yes yes 128 Mb
Quad SPI24 dual-parallel 0001 x8 yes yes 256 Mb
Quad SPI32 single or dual-stacked 5 0010 x1, x2, x4 yes yes 4 Gb
Quad SPI32 dual-parallel 0010 x8 yes yes 8 Gb
SD0 (3.0) 0011 x4 yes yes 8191 (for FAT files)
SD1 (2.0) 0101 x4 yes yes 8191 (for FAT files)
SD1 (3.0) 1110 x4 yes yes 8191 (for FAT files)
SelectMAP 4 1010 x8, x16, x32 yes no N/A
  1. Execute in place (XIP) is not supported by Versal devices.
  2. The legacy mode Linear Quad SPI (LQSPI) is not supported by Versal devices.
  3. The "search offset limit" is used when the BootROM executable is searching the boot device for a PDI with a boot header and a PLM. This is used for fallback boot and MultiBoot.
  4. JTAG and SelectMAP are supervised boot modes. Other devices provide autonomous boot modes.
  5. For dual-stacked QSPI, only the first flash device can be accessed during the BootROM stage.
  6. Primary boot on the eMMC0 is not supported.

When selecting a boot device to implement in a board design, it is important to consider the post-boot use of shared multiplexed I/O pins and the voltage requirements of each boot mode. For more information, refer to the Platform Management Controller section in the Versal Adaptive SoC Technical Reference Manual (AM011).

Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 Devices

For more information on Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices, refer to Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).

Table 2. Primary Boot Interfaces Table
Boot Interface Mode [3:0] Pins Secure Boot Capable Data Bus Width Description
Interfaces controlled by external devices (supervised)
JTAG² 0000 Yes x1 Dedicated JTAG interface, see JTAG Boot Mode in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).
SelectMAP 1010 Yes x8, x16, x32 SelectMAP parallel bus interface, see SelectMAP Boot Mode in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).
Interfaces controlled by on-chip controllers (autonomous)
OSPI 1000 Yes x8 OSPI interface supports single and dual-stacked flash devices, see QSPI Flash Boot Mode in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).
QSPI24 0001 Yes x1, x2, x4

(single or dual-stacked)

x8 (dual-parallel)
QSPI interface supports the x24 (3-byte) flash addresses(1).
QSPI32 0010 Yes x1, x2, x4

(single or dual-stacked)

x8 (dual-parallel)
QSPI interface supports the x32 (4-byte) flash addresses. x3 flash addressing is required to address flash devices that are greater than 128 Mb.(1)
eMMC v5.1 0110 Yes x4 eMMC v5.1 interface, see eMMC v5.1 Boot Mode.
SD v2.0 0101 Yes x4 SD v2.0 interface.
SD v3.0 first 0011 Yes x4 SD v3.0 interface (first pin out option), see SD Flash Boot Mode in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).
SD v3.0 second 1110 Yes x4 SD v3.0 interface (second pin out option), see SD Flash Boot Mode in Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).
UFS 1011 Yes GTs Universal flash storage v3.1 interface with gigabit transceiver interface.
Note: The UFS interface uses high-speed I/O transceivers that require on-board clocking circuitry.
  1. For quad SPI single flash or dual-stacked flash setups, only a subset of the MIO interface pins listed are required and the MIO interface pins can be used for other peripherals. See the boot interface diagrams for more information.