The application processing unit (APU) consists of an Arm Cortex-A78AE processor, L1 cache, L2 cache, L3 cache, and system-level caches, and related functionality. The Cortex-A78AE cores and caches are part of the Arm processor MPCore IP.
Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices has Cortex-A78AE cores implement Armv8 64-bit architecture.
The APU includes the following features:
- Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 have 1 MB L3 cache per cluster and a single 4MB SLC.
- L1 caches are 64 KB each
- 512 KB of L2 per core with ECC support
- GIC-600 interrupt controller
- Per core power-gating support
- TrustZone support
- Dot product instruction support
- Pointer authentication
- Extended pointer authentication
- Speculative barrier instructions
- Statistical Profiling Extension (SPE)
Important: The features in this
document apply to most Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices. For the 2VM3654 device in
the Versal Prime Series Gen 2, some features including APU
cluster configuration and cache details vary from those listed in this document. For
more detail on these differences, see the
Versal
Architecture and Product Data Sheet: Overview (DS950).