The application processing unit (APU) consists of an Arm Cortex-A78AE processor, L1 cache, L2 cache, L3 cache and related functionality.
It has Cortex-A78AE cores based on Armv8 64-bit architecture.
The APU includes the following features:
-
It has 1 MB L3 cache per cluster and a four 1MB SLC.
- L1 caches are 64 KB each
- 512 KB of L2 per core with ECC support
- GIC-600 interrupt controller
- Per core power-gating support
- TrustZone support
- Dot product instruction support
- Pointer authentication
- Extended pointer authentication
- Speculative barrier instructions
- Statistical Profiling Extension (SPE)
For more information about APU Subsystem, see Versal AI Edge Series Gen 2 and Prime Series Gen 2 Technical Reference Manual (AM026).
Important: The features in this
document apply to most Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices. For the 2VM3654 device in
the Versal Prime Series Gen 2, some features including APU
cluster configuration and cache details vary from those listed in this document. For
more detail on these differences, see the
Versal
Architecture and Product Data Sheet: Overview (DS950).