AI Engine Configuration - 2025.1 English - UG1304

Versal Adaptive SoC System Software Developers Guide (Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2) (UG1304)
Document ID
UG1304
Release Date
2025-06-23
Version
2025.1 English
Note: This section is not applicable to the Versal Prime Series Gen 2 and Versal AI Edge Series Gen 2 devices.

The AI Engine configuration consists of the following files.

Table 1. AI Engine Configuration
File Contents
AI Engine NPI CDO AI Engine Global Configuration using NPI
  • PLL configuration
  • AI Engine scan clear and memory clear using PM initialization node commands
AI Engine ELF AI Engine tile program and data memory
AI Engine CDO AI Engine array configuration
  • Program memory configuration
  • Data memory configuration
  • DMA, locks, stream switch configuration
  • AI Engine register module configuration

Before loading the AI Engine NPI CDO, ensure that PLM, LPD and PL (with NoC configuration in the NPI file) are completed. Also, enable the NoC path from the PMC to the AI Engine in the design for PLM to clear the AI Engine data memories.