AI Engine Clock Frequency Scaling - 2025.1 English - UG1304

Versal Adaptive SoC System Software Developers Guide (Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2) (UG1304)

Document ID
UG1304
Release Date
2025-06-23
Version
2025.1 English
Note: This feature is not applicable for Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices.

When a subsystem is using an AI Engine partition, it can request to increase or decrease the AI Engine clock frequency. The subsystem can use XPm_SetRequirement to change the clock frequency. The QoS argument is used to represent the divider value.

The following example call requests that the AI Engine clock divider be set to four:

XPm_SetRequirement(aie_node, PM_CAP_ACCESS, 4, REQUEST_ACK_NO)

The call to change the frequency is considered only a request and is fulfilled if no other AI Engine partitions are using a frequency higher than the requested divider value. The highest requested frequency from any subsystem for an AI Engine is fulfilled.

  • If the subsystem does not care what divider value is used, the QoS can be set to 0.
  • If the subsystem would like to reset to the original boot time divider value, the QoS can be set to 1.

Any QoS value that is less than the default divider value (boot time) resets the divider value to the default.