AI Engine Clock Frequency Scaling - AI Engine Clock Frequency Scaling - 2026.1 English - UG1304

Versal Adaptive SoC System Software Developers Guide (UG1304)

Document ID
UG1304
Release Date
2026-06-23
Version
2026.1 English

When a subsystem is using an AI Engine partition, it can request to increase or decrease the AI Engine clock frequency using the IOCTL_SET_AIE_CLK_DIV IOCTL (ID 40). The divider value is passed as the first argument.

The following example call requests that the AI Engine clock divider be set to four:

XPm_DevIoctl(aie_node, IOCTL_SET_AIE_CLK_DIV, 4, 0, 0, &Response)

The call to change the frequency is considered only a request and is fulfilled if no other AI Engine partitions are using a frequency higher than the requested divider value. The highest requested frequency from any subsystem for an AI Engine is fulfilled.

  • If the subsystem does not care what divider value is used, the divider can be set to 0.
  • If the subsystem would like to reset to the original boot time divider value, the divider can be set to 1.
  • Any divider value that is less than the default divider value (boot time) resets the divider value to the default.