Initially VIV was launched as a Tcl-based script (viv.tcl) and was not a part of the Vivado Design Suite which is distributed separately as an encrypted Tcl
file. To use viv.tcl IDF DRCs, users need to source the viv.tcl script to load DRCs into
Vivado. Refer to Vivado
Isolation Verifier User Guide (Tcl Based) (UG1290) for complete details. VIV has been
integrated with the Vivado Design Suite starting with the
2018.2 release to improve its performance. This new version of VIV is also referred to
as VIV2 in this document. Prior to Vivado version
2021.1, users needed to enable VIV by setting a parameter - hd.enableIDFDRC to True. But from Vivado
version 2021.1 onwards, VIV gets enabled automatically when the tool detects HD.ISOLATED property is set to True for any Vivado designs. For more details on HD.ISOLATED property, refer to
Isolation Design Flow for UltraScale+ FPGAs
and Zynq UltraScale+ MPSoCs (XAPP1335).