To facilitate isolation analysis, the usual FPGA flow has a new set of constraints to control routing and additional floorplanning requirements. Firstly, the design is manually floorplanned. Secondly, constraints are applied to isolated regions of the floorplan to follow strict rules. Finally, VIV is used to demonstrate to ensure that the design is correctly implemented.
The following figure shows where isolation analysis fits in to the usual FPGA development flow. VIV is useful at two levels:
- VIV helps to avoid costly circuit board layout mistakes during floorplanning (shown on the right side blue boxes) and helps document the floorplan, a key part of the isolation approach of the design.
- VIV proves that the design is isolated per IDF rules when the design is complete (shown on the lower right green boxes).
The flowchart notation is as follows:
- Boxes represent processes
- Parallelograms represent data
- Trapezoids (quadrilaterals with one pair of parallel sides) represent manual input
- Shapes with curved bottoms represent output
- Arrows represent information flow
- Color is used specifically for grouping and emphasis
Figure 1. Vivado Isolation Design Flow Relative to a Typical FPGA Design
Flow
