Proof of correctness is required for safety, security, and other high-reliability applications. The Isolation Design Flow (IDF) includes a set of design rule checks (DRCs) implemented by the AMD Vivado™ Isolation Verifier (VIV) that verifies the login ID and Vivado software have fulfilled the requirements of isolation design methodology (IDF) (see Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335).
This feature must be manually enabled, explicitly, (see Installation) because VIV is included with the Vivado Design Suite. When enabled, six additional DRCs appear under the Isolation category. The user invokes these DRCs, using the Vivado DRC interface like any other built-in DRCs. Results are provided in tabular form in the GUI with hyperlinks to design elements related to potential isolation violations. The VIV DRCs also contribute to the text-based output of the Vivado DRC reporting system.
VIV aids in board development by checking that I/O pin assignments, I/O bank assignments, and floorplanning range constraints do not violate IDF rules. This is in addition to offering proof of isolation. The intent of these design constraint checks spares the designer from costly printed circuit board redesigns.
- IDF_VIV2-1 provides provenance for VIV DRC results.
- IDF_VIV2-2, IDF_VIV2-3, and IDF_VIV2-4 checks the design constraints (pblocks, pads, pins, and banks).
- IDF_VIV2-5 and IDF_VIV2-6 checks the placement and routing of the implemented design.