IDF_VIV2-4 - Floorplan Violation

Isolated pblocks must be separated by a valid fence. The definition of a valid fence is detailed in the Isolation Design Flow documentation. Users must follow the documented rules for the appropriate technology. Refer to the applicable reference documents identified in References, page 24. See Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for additional details on fencing rules and see Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq 7000 SoCs (Vivado Tools) (XAPP1222) for 7 series fencing rules.

IDF_VIV2-4 checks that floorplan area ranges from distinct isolation Pblocks have an appropriate gap between them. IDF_VIV2-4 checks Derived Range information, not the XDC Range. For example, when the user gives in the XDC Range, Vivado computes internally the Derived Range by taking into account the Programmable Units and the Snapping Mode property of Pblock.

Important: IDF requires that users create designs with Snapping mode FINE_GRAINED. Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for detailed rules.

Note: From 2019.2 onwards default value of SNAPPING_MODE for Isolated s is FINE_GRAINED.

Note: PU and Snapping Mode concept needs to be taken into account only for UltraScale+ architecture and not 7 Series.

The following example shows all of the constraints present in an XDC file that are needed to create a floorplan of an isolated function, into a specific region of the device (using pblocks).

create_pblock pblock_zup_ISO_Wrapper
add_cells_to_pblock [get_pblocks pblock_zup_ISO_Wrapper] [get_cells -quiet [list
design_1_i/zup_ISO_Wrapper]]
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add {SLICE_X14Y150:SLICE_X15Y179
SLICE_X13Y125:SLICE_X13Y179 SLICE_X13Y35:SLICE_X13Y54 SLICE_X0Y0:SLICE_X12Y179}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add
{BUFCE_LEAF_X64Y8:BUFCE_LEAF_X87Y11 BUFCE_LEAF_X0Y0:BUFCE_LEAF_X63Y11}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add
{BUFCE_ROW_FSR_X12Y2:BUFCE_ROW_FSR_X16Y2 BUFCE_ROW_FSR_X0Y0:BUFCE_ROW_FSR_X11Y2}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add
{BUFGCE_HDIO_X0Y4:BUFGCE_HDIO_X1Y5}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add {BUFG_PS_X0Y0:BUFG_PS_X0Y71}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add {DSP48E2_X0Y0:DSP48E2_X0Y71}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add
{HARD_SYNC_X2Y4:HARD_SYNC_X3Y5 HARD_SYNC_X0Y0:HARD_SYNC_X1Y5}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add
{HDIOBDIFFINBUF_X0Y30:HDIOBDIFFINBUF_X0Y35}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add
{HDIOLOGIC_M_X0Y30:HDIOLOGIC_M_X0Y35}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add
{HDIOLOGIC_S_X0Y30:HDIOLOGIC_S_X0Y35}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add
{HDIO_BIAS_X0Y2:HDIO_BIAS_X0Y2}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add {IOB_X0Y130:IOB_X0Y141}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add {PS8_X0Y0:PS8_X0Y0}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add {RAMB18_X1Y50:RAMB18_X1Y71
RAMB18_X1Y14:RAMB18_X1Y21 RAMB18_X0Y0:RAMB18_X0Y71}
resize_pblock [get_pblocks pblock_zup_ISO_Wrapper] -add {RAMB36_X1Y25:RAMB36_X1Y35
RAMB36_X1Y7:RAMB36_X1Y10 RAMB36_X0Y0:RAMB36_X0Y35}
set_property SNAPPING_MODE FINE_GRAINED [get_pblocks pblock_zup_ISO_Wrapper]
set_property HD.ISOLATED true [get_cells */zup_ISO_Wrapper]
set_property HD.ISOLATED_EXEMPT true [get_cells -hierarchical -filter {
PRIMITIVE_TYPE == CLOCK.BUFFER.BUFGCE }]
set_property HD.ISOLATED_EXEMPT true [get_cells -hierarchical -filter
{PRIMITIVE_TYPE =~ CLOCK.BUFFER.BUFG_PS}]
set_property HD.ISOLATED_EXEMPT true [get_cells -hierarchical -filter {
PRIMITIVE_TYPE == CLOCK.BUFFER.BUFGCE }]

A violation of IDF_VIV2-4 takes two forms:

Tile adjacency violation: pblock: <pblock name> tile: <tile name> vs pblock: <pblock
name> tile: <tile name>. Sites: <site name list>.

and

Tile occupancy violation: tile: <tile name> is in multiple isolated pblocks: <pblock
name list>. Sites: <site name list>.

IDF_VIV2-4 - Floorplan Violation - UG1291

Vivado Isolation Verifier User Guide (UG1291)