IDF_VIV2-1 is an advisory DRC documenting the circumstances of the run. It also validates that the design has at least two pblocks marked as isolated (using the HD.ISOLATED property). Nets driven by cells marked HD.ISOLATED_EXEMPT are exempt from inter-region isolation rules and are listed in the IDF_VIV2-1 output.
Here is an example of IDF_VIV2-1 output:
Vivado Isolation Verifier v2.0 (20180514)
Copyright (C) 2013-2018 Xilinx, Inc. All rights reserved.
Date(GMT): Tue May 15 12:50:38 2018
Top-level: design_1_wrapper
Isolated Partitions: pblock_uram_top_0 pblock_uram_top_1 pblock_uram_top_2
Part: xcvu13p-flga2577-1-i
Directory: c:/xilinx_design/implementation/idflab
User: <username>
Vivado Version: 2018.2
Platform: lnx64
Host: <hostname>
Top Level nets: CE_0, CE_1, CE_2, SCLR_0, SCLR_1, SCLR_2, clka_0, ena_0, clka_1,
clka_2, ena_1, ena_2, regcea_0, regcea_1, regcea_2 (the first 15 of 210 listed)
HD.ISOLATED_EXEMPT nets:
design_1_i/ps7_ISO_Wrapper/processing_system7_0/inst/FCLK_CLK0,
design_1_i/ps7_ISO_Wrapper/processing_system7_0/inst/FCLK_CLK1 and
design_1_i/ps7_ISO_Wrapper/processing_system7_0/inst/FCLK_CLK2.
Inter-region nets:
design_1_i/keccak_0_ISO_Wrapper/buffer_data_reg[0]_0_ISOBUF_pblock_keccakCompare_0_
NewDrv,
M
design_1_i/ps7_ISO_Wrapper/processing_system7_0/inst/FCLK_CLK0,
design_1_i/ps7_ISO_Wrapper/processing_system7_0/inst/FCLK_CLK1,
design_1_i/ps7_ISO_Wrapper/processing_system7_0/inst/FCLK_CLK2,
design_1_i/ps7_ISO_Wrapper/processing_system7_0/inst/FCLK_RESET0_N and
design_1_i/ps7_ISO_Wrapper/processing_system7_0/inst/FCLK_RESET1_N.Note: For UltraScale+ architecture, IDF_VIV2-1
gives an error if there are any pblocks with Snapping Mode property not set to
FINE_GRAINED.