A field programmable gate array (FPGA) contains logic elements and routing. Both are controlled by configuration memory programmed by the user. Logic elements range in complexity from simple combinatorial logic functions up to complete embedded processors. Logic elements and routing are arrayed in a grid of tiles. The structure of an FPGA is extremely regular. Each tile contains one of a small variety of VLSI circuits dedicated to logic or routing.
- Configurable logic blocks (CLBs) contains a small amount of programmable logic and memory
- Input/output block circuitry (IOBs).
- Clock Management Tiles (CMTs)
- Other specialized circuitry that includes block RAMs, digital signal processors (DSPs), processors, etc.
Typically, AMD FPGA have thousands of tiles, but only dozens of tile types. Common to all tiles is their association to a Global Switch Matrix (GSM). The GSM is composed of many interconnect tiles and interface tiles. Some logic tiles such as CLBs are associated with one interconnect tile, whereas other tiles such as block RAMs and DSPs are associated with multiple interconnect tiles. Interface tiles are used to adapt the various types of logic tiles to the common interconnect tile design.
In 7 series architectures, each user tile has a dedicated interconnect tile but UltraScale+™ architecture is different, as user tiles share interconnect tiles. In UltraScale+ devices two CLEs share one interconnect tile or one block RAM shares five interconnects with five CLEs, thus introducing the Programmable Unit (PU). The PU is a set of tiles that shares interconnect tiles. For example, two CLEs that share one interconnect tile is one PU. It is the same as one block RAM with five CLEs that share five interconnect tiles, and constitutes one PU. See Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for more details on PU and UltraScale+ Architecture specific IDF concepts.
An FPGA is configured for a particular purpose by loading configuration memory with a particular bitstream. The bitstream specifies the exact function of each and every tile in the device. Whether used or not, logic tiles are configured to perform a specific function and the GSM is configured to provide the required routing between the logic tiles.