Many of the terms in this document are used in a specialized sense. The following glossary helps readers who are not well versed with Xilinx terminology related to FGPA architecture and configuration, or search algorithms.
- Area Range
- List of rectangular regions identifying a subset of the device resources in an FPGA. It is defined as a list of resource pairs in an XDC file. Each pair defines two opposite corners of an included rectangular region.
- Bitstream
- Contiguous sequence of bits that represents a stream of data..
- FPGA Bitstream
- File that contains the programming information for an FPGA. A AMD FPGA device must be programmed using a specific bitstream in order for it to behave as an embedded hardware platform. This bitstream is typically provided by the hardware designer who creates the embedded platform. Programming an FPGA is the process of loading a bitstream into the FPGA. During the development phase, the FPGA is programmed using utilities such as AMD Vivado™ or using menu options in SDK. These tools transfer the bitstream to the FPGA on board. The bitstream is usually placed in non-volatile memory in the production hardware which is configured to program the FPGA when powered on..
- Device Model
- Data and data structures that describe the potential programming of a specific model of an FPGA. The device model specifies the capacity of the device and all of the features that can be configured to realize an FPGA design. The device model is highly abstracted from the FPGA hardware schematics. Only aspects of the FPGA hardware that are programmable are represented. Although it is theoretically possible that a programmable feature of an FPGA might not be represented in the device model (for example, if testing shows the feature to be unreliable), in practice this is not applicable because it would make it impossible to perform the tests that would validate or invalidate the feature.
- Programmable Unit (PU)
- Set of logical tiles such as CLEs, BRAMs, DSPs along with their shared interconnect tiles (one block RAM, five CLEs, and five interconnect tiles shared between block RAM and CLEs are one PU). When reserving resources during floorplanning it is strongly recommended to take the whole PU in the pblock. See Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for more details on PU.
- Fence Tile / PU
- Un-programmed tiles or PU, free of routing or logic, which is used to
separate two or more tiles or PUs containing logic or routing from distinct
isolated modules.Note: Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for fencing rules with respect to UltraScale+ architecture, and Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq 7000 SoCs (Vivado Tools) (XAPP1222) for fencing rules with respect to 7-series FPGAs.
- Function Module
- Collection of logic that performs a specific operation, for example an encryption circuit..
- Interconnect Tile
- Common hard IP block providing a programmable switching matrix connecting programmable logic elements of virtually all types to routing resources. The interconnect blocks are collectively referred to as the Global Switching Matrix in the end user documentation. Typically, individual interconnect blocks are not referred to in the documentation, but might occasionally be referred to as switch boxes.
- Inter-Region Signal
- Non-isolated net with one source and one load typically connects one isolated function/module to another, though sometimes connects one port of an isolated module to another port of the same isolated module or to top-level logic. An inter-region signal is not permitted to use routing resources containing programmable interconnect points (PIPs) in fence.
- Isolation
- Free from unintended influence. For the case of routing, the degree isolation is measured by the number of switch failures required to establish an unintended signal path between isolated circuits. For the case of floorplanning, isolation is determined by the presence of a “fence” of tiles/PUs free of isolated logic and routing between isolated portions of the design..
- Isolated Function, Isolated Module
- Portion of the custom design that is intended to be isolated.
- Isolated Region, Isolated
- Collection of tiles defined by area range constraints that can be used when implementing an isolated module.
- Isolated Region, Isolated
- Collection of tiles defined by area range constraints that can be used when implementing an isolated module.
- I/O Buffer, IOB
- Circuit in an FPGA that controls the behavior of the input/output pins on the FPGA package. An I/O buffer controls various communication-related settings, such as whether an associated pin is connected internally to an input circuit or an output circuit, or selects the voltage level expected by the pin.
- I/O Bank
- Collection of I/O buffers in an FPGA for settings and signals, common to the collection.
- Logic
- Circuits that implement a specific function; a flip-flop, look up table, and random access memory.
- Net
- Named collection of routing resources that creates signal paths among a collection of logic elements. A net can span levels in the design hierarchy.
- Node
- Indivisible unit of programmable routing. A node can branch out to connect more than two points.
- Package Pin
- Conductor on the outside of an FPGA package that powers or interfaces with the FPGA. It is shaped like a short wire protruding perpendicularly from the chip package, or shaped like a bump.
- Partition
- Defined collection of logic that isolates one piece of hierarchy from another.
- Placement
- Assignment of a logical function to specific hardware resources.
- Derived Range
- Derived range is the pblock boundary after considering all the tiles of the Programable Units (PU) in that Pblock. When Snapping Mode property of a Pblock is set to OFF, both derived and XDC range compute the same pblock boundary. When Snapping Mode property of a Pblock is set to FINE_GRAINED, the derived range might be different than the user-specified XDC range. If Snapping Mode is set to FINE_GRAINED, and if some of the tiles of a PU are left off in the XDC range, all of the tiles in that PU are excluded from the Pblock boundary in the derived range.
- Derived Range
- Derived range is the pblock boundary after considering all the tiles of the
Programable Units (PU) in that pblock. When Snapping Mode property of a pblock
is set to OFF, then both derived and XDC range compute the same pblock boundary.
When Snapping Mode property of a pblock is set to FINE_GRAINED, the derived
range might be different than the user-specified XDC range. If Snapping Mode is
set to FINE_GRAINED, and if some of the tiles of a PU are left off in the XDC
range, then all of the tiles in that PU are excluded from the pblock boundary in
the derived range.Note: IDF requires FINE_GRAINED as the Snapping Mode property of pblocks. See Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for more details.Note: Programmable Unit and Derived Range concepts are applicable with respect to UltraScale+ architecture.
- Route
- Path that a signal follows within an FPGA as represented by a collection of nodes connected to one another by programmable interconnect points (PIPs).
- Site
- Physical location in the FPGA tile array that can be referenced in the floorplanning constraints, such as a SLICE, or RAMB16, etc.
- Switch Matrix, Global Switch Matrix, GSM
- Aggregate term for a programmable routing. The GSM is primarily composed of interconnect blocks..
- Trusted Routing
- Connects isolated functions using routing resources with no programmable interconnection points within fence tiles. Trusted Routing is generated automatically without manual placement. Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for more details.
- Xilinx Design Constraints, XDC
- SDC-based constraints in Tcl notation describing aspects of the design that includes floorplanning, pin assignments, electrical properties of I/O signals, and timing characteristics, but not the logic of the design.
- Wire
- Conductive path in a chip along which signals or power flow. A wire is the hardware that implements the node abstraction. The term wire also describes the software device model for a portion of a node that occupies exactly one tile.