Constraint Checking (VIV – Constraints) - UG1291

VIV checks the following on the pin constraints and floorplan: .

• Pins from different isolation pblocks are not co-located in an I/O bank. This is checked in IDF_VIV2-2.
  Note: While VIV does report I/O bank sharing as a violation, this is a security precaution. - not mandated by analysis. The majority of applications allow for sharing of banks. Designers need to decide on a case-by-case basis if their design allows I/O bank sharing.
• Pins from different isolation pblocks are not physically adjacent on the package. Pins are considered adjacent if they share an edge or corner with no fence tile (unconstrained package pin) between them. This is checked in IDF_VIV2-3.
• The Pblock constraints in the XDC file are defined such that a minimum of a one tile/PU wide fence exists between isolated regions. This is checked in IDF_VIV2-4.
  Note: For UltraScale+ architecture, fence is unprogrammed PUs and for 7 series FPGAs, fence is unprogrammed tile.
  Note: Refer to Isolation Design Flow for UltraScale+ FPGAs and Zynq UltraScale+ MPSoCs (XAPP1335) for UltraScale+ architecture, and Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq 7000 SoCs (Vivado Tools) (XAPP1222) for 7 series FPGA.

Because placement information is not used, VIV assumes 100% utilization of all constrained resources so that whatever resources are used in the implemented design, an isolation violation cannot occur.