QSFP28 Module Connector - QSFP28 Module Connector

The Alveo accelerator cards host two 4-lane small form-factor pluggable (QSFP) connectors that accept an array of optical modules. Each connector is housed within a single QSFP cage assembly. Note QSFP0 is port 1, the upper port located on the PCIe bracket and QSFP1 is port 2, the lower port located on the PCIe bracket, closest to the PCIe card edge fingers.

Refer to the section for the FPGA clock sources. The detailed device and QSFP pin connections for the feature described in this section are documented in the XDC file found in the Getting Started tab of the respective product page:

The QSFP+ connectors are accessible via the I2C interface on the Alveo U200/U250 accelerator cards. The QSFP connector’s sideband signals are accessible directly from the FPGA. The MODSELL, RESETL, MODPRSL, INTL, and LPMODE sideband signals are defined in the following small form factor (SFF) specifications.

For additional information about the quad SFF pluggable (28 Gb/s QSFP+) module, see the SFF-8663 and SFF-8679 specifications for the 28 Gb/s QSFP+ at the SNIA Technology Affiliates website: https://www.snia.org/sff/specifications2.

QSFP0

The QSFP0 interface has the high-speed connections to the UltraScale+ device listed in the following table.

Table 1. QSFP0 Interface High-Speed Connections
Name	Direction	Bank	I/O Reference	Pin	Description
MGT_SI570_CLOCK0_C_N	Input	231	MGTREFCLK0N_231	M10	REFCLK0 Negative LVDS Signal
MGT_SI570_CLOCK0_C_P	Input	231	MGTREFCLK0P_231	M11	REFCLK0 Positive LVDS Signal
QSFP0_CLOCK_N	Input	231	MGTREFCLK1N_231	K10	REFCLK1 Negative LVDS Signal
QSFP0_CLOCK_P	Input	231	MGTREFCLK1P_231	K11	REFCLK1 Positive LVDS Signal
QSFP0_RX1_N	Input	231	MGTYRXN0_231	N3	Negative Receive Lane 1 Input
QSFP0_RX2_N	Input	231	MGTYRXN1_231	M1	Negative Receive Lane 2 Input
QSFP0_RX3_N	Input	231	MGTYRXN2_231	L3	Negative Receive Lane 3 Input
QSFP0_RX4_N	Input	231	MGTYRXN3_231	K1	Negative Receive Lane 4 Input
QSFP0_RX1_P	Input	231	MGTYRXP0_231	N4	Positive Receive Lane 1 Input
QSFP0_RX2_P	Input	231	MGTYRXP1_231	M2	Positive Receive Lane 2 Input
QSFP0_RX3_P	Input	232	MGTYRXP2_231	L4	Positive Receive Lane 3 Input
QSFP0_RX4_P	Input	231	MGTYRXP3_231	K2	Positive Receive Lane 4 Input
QSFP0_TX1_N	Output	231	MGTYTXN0_231	N8	Negative Transmit Lane 1 Output
QSFP0_TX2_N	Output	231	MGTYTXN1_231	M6	Negative Transmit Lane 2 Output
QSFP0_TX3_N	Output	231	MGTYTXN2_231	L8	Negative Transmit Lane 3 Output
QSFP0_TX4_N	Output	231	MGTYTXN3_231	K6	Negative Transmit Lane 4 Output
QSFP0_TX1_P	Output	231	MGTYTXP0_231	N9	Positive Transmit Lane 1 Output
QSFP0_TX2_P	Output	231	MGTYTXP1_231	M7	Positive Transmit Lane 2 Output
QSFP0_TX3_P	Output	231	MGTYTXP2_231	L9	Positive Transmit Lane 3 Output
QSFP0_TX4_P	Output	231	MGTYTXP3_231	K7	Positive Transmit Lane 4 Output

QSFP1

The QSFP1 interface has the high-speed connections to the UltraScale+ device listed in the following table.

Table 2. QSFP1 Interface High-Speed Connections
Signal Name	Direction	Bank	I/O Reference	Pin	Description
MGT_SI570_CLOCK1_C_N	Input	230	MGTREFCLK0N_230	T10	REFCLK0 Negative LVDS Signal
MGT_SI570_CLOCK1_C_P	Input	230	MGTREFCLK0P_230	T11	REFCLK0 Positive LVDS Signal
QSFP1_CLOCK_N	Input	230	MGTREFCLK1N_230	P10	REFCLK1 Negative LVDS Signal
QSFP1_CLOCK_P	Input	230	MGTREFCLK1P_230	P11	REFCLK1 Positive LVDS Signal
QSFP1_RX1_N	Input	230	MGTYRXN0_230	U3	Negative Receive Lane 1 Input
QSFP1_RX2_N	Input	230	MGTYRXN1_230	T1	Negative Receive Lane 2 Input
QSFP1_RX3_N	Input	230	MGTYRXN2_230	R3	Negative Receive Lane 3 Input
QSFP1_RX4_N	Input	230	MGTYRXN3_230	P1	Negative Receive Lane 4 Input
QSFP1_RX1_P	Input	230	MGTYRXP0_230	U4	Positive Receive Lane 1 Input
QSFP1_RX2_P	Input	230	MGTYRXP1_230	T2	Positive Receive Lane 2 Input
QSFP1_RX3_P	Input	230	MGTYRXP2_230	R4	Positive Receive Lane 3 Input
QSFP1_RX4_P	Input	230	MGTYRXP3_230	P2	Positive Receive Lane 4 Input
QSFP1_TX1_N	Output	230	MGTYTXN0_230	U8	Negative Transmit Lane 1 Output
QSFP1_TX2_N	Output	230	MGTYTXN1_230	T6	Negative Transmit Lane 2 Output
QSFP1_TX3_N	Output	230	MGTYTXN2_230	R8	Negative Transmit Lane 3 Output
QSFP1_TX4_N	Output	230	MGTYTXN3_230	P6	Negative Transmit Lane 4 Output
QSFP1_TX1_P	Output	230	MGTYTXP0_230	U9	Positive Transmit Lane 1 Output
QSFP1_TX2_P	Output	230	MGTYTXP1_230	T7	Positive Transmit Lane 2 Output
QSFP1_TX3_P	Output	230	MGTYTXP2_230	R9	Positive Transmit Lane 3 Output
QSFP1_TX4_P	Output	230	MGTYTXP3_230	P7	Positive Transmit Lane 4 Output

QSFP28 Module Connector - QSFP28 Module Connector - UG1289

Alveo U200 and U250 Accelerator Cards User Guide (UG1289)

QSFP0

QSFP1