Miscellaneous I/O - Miscellaneous I/O - UG1289

Alveo U200 and U250 Accelerator Cards User Guide (UG1289)
Document ID
UG1289
Release Date
2023-06-13
Revision
1.1 English

On the U200 and U250 cards, the UltraScale+ device has a single bank with various inputs and outputs to communicate with the satellite controller and other devices on the card. See the XDC file for all of the signal connections. This section only references the signals that are usable in bank 64. Bank 64 is powered from a 1.2V source. Care needs to be taken when using the LVDS Clocks on a 1.2V bank. A DQS_BIAS needs to be used or another IO standard which re-biases the signals internal to the part similar to the SSTL12 standard because there are no rebiasing resistors on the input signal.

Table 1. Bank 64 Miscellaneous I/O Descriptions
Signal Name Direction Pin I/O Description
USB_UART_RX Output BB20 IO_T3U_N12_64 UART Output to FTDI FT4232 RX input
USB_UART_TX Input BF18 IO_L24N_T3U_N11_64 UART Input from FTDI FT4232 TX output
PCIE_PERST_LS Input BD21 IO_L23P_T3U_N8_64 Active-Low input from connector to FPGA to detect presence.
QSFP0_MODSELL_LS Output BE16 IO_L22N_T3U_N7_DBC_AD0N_64 QSFP, Active-Low, Module Select
QSFP0_RESETL_LS Output BE17 IO_L22P_T3U_N6_DBC_AD0P_64 QSFP, Active-Low, Module Reset
QSFP0_MODPRSL_LS Input BE20 IO_L21N_T3L_N5_AD8N_64 QSFP, Active-Low, Module Present
QSFP0_INTL_LS Input BE21 IO_L21P_T3L_N4_AD8P_64 QSFP, Active-Low, Module Interrupt Output to FPGA
QSFP0_LPMODE_LS Output BD18 IO_L20N_T3L_N3_AD1N_64 QSFP, Active-Low, Low Power Mode Enable. Must be High for normal operation.
I2C_MAIN_RESET_B_LS Input BF19 IO_L19N_T3L_N1_DBC_AD9N_64 Reset from Satellite controller (SC) to reset I2C MUX
I2C_FPGA_SCL_LS Input BF20 IO_L19P_T3L_N0_DBC_AD9P_64 Slave I2C data connection from satellite controller to FPGA.
I2C_FPGA_SDA_LS Bidirectional BF17 IO_T2U_N12_64 Slave I2C clock connection from satellite controller to FPGA.
FPGA_TXD_MSP Output BB19 IO_L18N_T2U_N11_AD2N_64 Satellite controller CMS UART receive (115200, no parity, 8 bits, 1 stop bit).
FPGA_RXD_MSP Input BA19 IO_L18P_T2U_N10_AD2P_64 Satellite controller CMS UART transmit (115200, no parity, 8 bits, 1 stop bit).
STATUS_LED0_FPGA Input BC21 IO_L17N_T2U_N9_AD10N_64 LED, Active High, Front Panel orange LED. Can also be driven by SC!
STATUS_LED1_FPGA Input BB21 IO_L17P_T2U_N8_AD10P_64 LED, Active High, Front Panel yellow LED. Can also be driven by SC!
STATUS_LED2_FPGA Input BA20 IO_L16N_T2U_N7_QBC_AD3N_64 LED, Active High, Front Panel green LED. Can also be driven by SC!
QSFP1_MODSELL_LS Output AY20 IO_L16P_T2U_N6_QBC_AD3P_64 QSFP, Active-Low, Module Select.
QSFP1_RESETL_LS Output BC18 IO_L15N_T2L_N5_AD11N_64 QSFP, Active-Low, Module Reset.
QSFP1_MODPRSL_LS Input BC19 IO_L15P_T2L_N4_AD11P_64 QSFP, Active-Low, Module Present.
QSFP1_INTL_LS Input AV21 IO_L14N_T2L_N3_GC_64 QSFP, Active-Low, Module Interrupt Output to FPGA.
QSFP1_LPMODE_LS Output AV22 IO_L14P_T2L_N2_GC_64 QSFP, Active-Low, Low Power Mode Enable. Must be High for normal operation.
USER_SI570_CLOCK_N Input AV19 IO_L12N_T1U_N11_GC_64 LVDS Reference Clock Input, Default is 156.25 MHz. Negative Signal.
USER_SI570_CLOCK_P Input AU19 IO_L12P_T1U_N10_GC_64 LVDS Reference Clock Input, Default is 156.25 MHz. Positive Signal.
SYSCLK1_300_N Input AW19 IO_L11N_T1U_N9_GC_64 LVDS Reference Clock Input, 300 MHz. Negative Signal.
SYSCLK1_300_P Input AW20 IO_L11P_T1U_N8_GC_64 LVDS Reference Clock Input, 300 MHz. Positive Signal.
QSFP0_FS0 Output AT20 IO_L10P_T1U_N6_QBC_AD4P_64 SI5335A Frequency Select Signal. FS[1:0] = 01 -> CLK1A/1B: 156.25 MHz 1.8V LVDS FS[1:0] = 1X -> CLK1A/1B: 161.1328125 MHz 1.8V LVDS
QSFP0_FS1 Output AU22 IO_L9N_T1L_N5_AD12N_64 SI5335A Frequency Select Signal. FS[1:0] = 01 -> CLK1A/1B: 156.25 MHz 1.8V LVDS FS[1:0] = 1X -> CLK1A/1B: 161.1328125 MHz 1.8V LVDS
QSFP0_REFCLK_RESET Output AT22 IO_L9P_T1L_N4_AD12P_64 SI5335A Active-Low, Reset Input to Clock Synthesizer.
QSFP1_REFCLK_RESET Output AR21 IO_L8N_T1L_N3_AD5N_64 SI5335A Active-Low, Reset Input to Clock Synthesizer.
QSFP1_FS0 Output AR22 IO_L8P_T1L_N2_AD5P_64 SI5335A Frequency Select Signal. FS[1:0] = 01 -> CLK1A/1B: 156.25 MHz 1.8V LVDS FS[1:0] = 1X -> CLK1A/1B: 161.1328125 MHz 1.8V LVDS.
QSFP1_FS1 Output AU20 IO_L7N_T1L_N1_QBC_AD13N_64 SI5335A Frequency Select Signal. FS[1:0] = 01 -> CLK1A/1B: 156.25 MHz 1.8V LVDS FS[1:0] = 1X -> CLK1A/1B: 161.1328125 MHz 1.8V LVDS.
DDR4_RESET_GATE Output AU21 IO_L7P_T1L_N0_QBC_AD13P_64 DDR4_RESET_GATE active-High output from FPGA to hold all external DDR4 interfaces in self-refresh. This output disconnects the memory interface reset and holds it in active and pulls the clock enable signal on the memory interfaces.