Zynq UltraScale+ MPSoC Register Initialization Table - Zynq UltraScale+ MPSoC Register Initialization Table - 2026.1 English

Zynq UltraScale+ MPSoC Register Initialization Table - Zynq UltraScale+ MPSoC Register Initialization Table - 2026.1 English - UG1283

Bootgen User Guide (UG1283)

Document ID

UG1283

Release Date

2026-06-23

Version

2026.1 English

The Register Initialization Table in Bootgen is a structure of 256 address-value pairs used to initialize PS registers for MIO multiplexer and flash clocks. For more information, see Initialization Pairs and INT File Attribute.

Table 1. Zynq UltraScale+ MPSoC Register Initialization Table
Address Offset	Parameter	Description
`0xB8` to `0x8B4`	Register Initialization Pairs: `<address>:<value>:` (2048 bytes)	If you set the Address to 0xFFFFFFFF, the system skips that register and ignores the value. All unused register fields must be set to Address=`0xFFFFFFFF` and value =`0x0`.