This section describes the boot and configuration sequence for Zynq 7000 SoC devices. See the Zynq 7000 SoC Technical Reference Manual (UG585) for more details on the available first stage boot loader (FSBL) structures.
BootROM on Zynq 7000 SoC
The BootROM is the first software to run in the application processing unit (APU). BootROM executes on the first Cortex® processor, A9-0, while the second processor, Cortex, A9-1, executes the wait for event (WFE) instruction. The main tasks of the BootROM are to configure the system, copy the FSBL from the boot device to the on-chip memory (OCM), and then branch the code execution to the OCM.
Optionally, you can execute the FSBL directly from a Quad-SPI or NOR device in a non-secure environment. The master boot device holds one or more boot images. The boot header and the first stage boot loader (FSBL) make up a boot image. Additionally, a boot image can include programmable logic (PL), a second stage boot loader (SSBL), and an embedded operating system and applications. However, the BootROM does not access these components. The boot mode pin strap settings, the boot header, and the system's characteristics affect the BootROM execution flow. The BootROM can execute in a secure environment with encrypted FSBL, or a non-secure environment. The supported boot modes are:
- Use JTAG mode primarily for development and debug.
- The device boots from NAND, parallel NOR, Serial NOR (Quad-SPI), and secure
digital (SD) flash memories.
The Zynq 7000 SoC Technical Reference Manual (UG585) provides the details of these boot modes. See Answer Record 52538 for answers to common boot and configuration questions.