Stacked Silicon Interconnect Technology (SSI technology) is used to break through the limitations of Moore’s law and deliver the capabilities to satisfy the most demanding design requirements.
A SSI technology device consists of multiple super logic region (SLRs), where each SLR is one die. SLR0, also referred to as Master SLR, is the bottom die. SLR1 is second from bottom, SLR2 is third from bottom and so on. An AMD Versal™ adaptive SoC SSI technology variants can have a maximum of four SLRs.
Each SLR has its own platform management controller (PMC) and a programmable logic (PL) region like a monolithic Versal adaptive SoC, but the slave SLRs do not have AI Engine and processing system (PS) regions.
The final PDI to boot on this device is a PDI of PDIs. Because each SLR has its own PMC block, each SLR boots with a PDI which is integrated in the main PDI.
- PLM elf in each SLR should be same.
- The BIF for Versal adaptive SoCs with SSI technology is different from its monolithic variant. Below is an example bif with two SLR devices.
- The whole BIF code block below goes into a Single file. Bootgen reads multiple BIF blocks and creates respective PDIs based on the BIF labels. These BIF block labels are referenced in master BIF, based on which Bootgen merges the individual PDIs into a master PDI. This master PDI alone is sufficient to boot an SSI technology device.
- The Slave SLRs uses the special
smap_width=0option indicating downstream connection and must not be changed.