In a PL-only design, to include Arm Cortex-A72 and Cortex-R5 in the power down mode, remove the FPD and LPD CDOs from the default (generated by Vivado) BIF, and re-generate the PDI.
The following is an example BIF with FPD and LPD CDOs removed:
new_bif:
{
id_code = 0x14ca8093
extended_id_code = 0x01
id = 0x2
image
{
name = pmc_subsys
id = 0x1c000001
partition
{
id = 0x01
type = bootloader
file = gen_files\plm.elf
}
partition
{
id = 0x09
type = pmcdata, load = 0xf2000000
file = gen_files\pmc_data.cdo
}
}
image
{
name = lpd
id = 0x4210002
partition
{
id = 0x0B
core = psm
file = static_files\psm_fw.elf
}
}
image
{
name = pl_cfi
id = 0x18700000
partition
{
id = 0x03
type = cdo
file = design_1_wrapper.rcdo
}
partition
{
id = 0x05
type = cdo
file = design_1_wrapper.rnpi
}
}
} Use the following command to re-generate PDI:
bootgen -arch versal -image filename.bif -w -o boot.pdi