The XPIO in Versal adaptive SoCs are similar to the high-speed I/O (HPIO) in the AMD UltraScale™ architecture. The XPIO are at the bottom and/or top periphery of the device. This differs from the I/O columnar layout in previous devices. The XPIO provide XPHY logic that is similar to UltraScale device native mode. The XPHY logic encapsulates calibrated delays along with serialization and deserialization logic for six single-ended I/O ports known as nibble.
Each XPIO bank contains nine XPHY logic sites and supports up to 54 single-ended I/O ports. Integrated DDR memory controller, soft memory controllers, and custom high-performance I/O interfaces use the XPHY logic. For more information on the XPIO, refer to the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).