The X5IO banks are similar to the high-speed I/O (HPIO) in the AMD UltraScale™ architecture. The X5IO sit at the bottom periphery. Previous devices used an I/O columnar layout. The X5IO provide X5IO PHY that is similar to UltraScale device native mode. The X5IO PHY encapsulates calibrated delays along with serialization and deserialization logic for eight single-ended I/O ports known as octad.
Each X5IO bank contains eight octad logic sites and supports up to 64 single-ended I/O ports. Integrated DDR memory controller, soft memory controllers, and custom high-performance I/O interfaces use the X5IO PHY. For more information on the X5IO, refer to the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).