The Vivado Design Suite is a key component in all Versal adaptive SoC design flows. Following are the primary use models for the Vivado tools based on your design flow:
- Traditional design flows
- Creating RTL and IP designs
- Platform-based design flows
- Creating and packaging RTL kernels for use in the Vitis environment design flow
- Creating and generating platforms for use in the Vitis environment design flow
Important: AMD provides standard platforms as starting points for the platform-based design flow. The Vivado IP integrator can customize and regenerate these to better fit the target system application. For more information, refer to the Vitis Embedded Platforms tab of the Downloads page on the AMD website.
You can use the Vivado tools for design creation, implementation, and analysis of PL. Typical tasks include the following:
- Logic simulation
- Constraint definition and timing analysis
- NoC compilation
- I/O and clock planning
- Logic synthesis and implementation
- Visualization of design logic
- Design rule checks (DRC) and design methodology checks
- Implementation results analysis
- Power and thermal analysis
- Programming and debugging
Creating RTL and IP Designs
The Vivado tools support the traditional RTL and IP design flow, and the Vivado IP integrator is available to automate the assembly of your design. RTL developers must understand the new IP available in Versal adaptive SoC and the requirements surrounding their usage. Consider the following conditions.
- All designs require the CIPS/PS Wizard IP, which contains the PMC used to boot the device. Also, CIPS IP configures the PS peripherals and the SYSMON IP. For more information, refer to the following documents:
- The only way to access the DDR memory controllers on the device is through the NoC IP. For more information, refer to the following documents:
- Hardware debug flows are different from previous devices. For more information, refer to the Vivado Design Suite User Guide: Programming and Debugging (UG908).
Creating and Packaging RTL Kernels
You can use the Vivado tools to package RTL kernels for use by the Vitis linker. This option is available in the Vivado IP packager, which packages the IP into an XO file. The Vitis system linker links this file into the final design. For more information about RTL kernels, including restrictions, refer to this link in the Data Center Acceleration using Vitis (UG1700).
Creating and Generating Platforms
AMD recommends the following:
- Include only essential Versal adaptive
SoC blocks and board interface IP in the platform
- Essential blocks: CIPS, PS wizard, NoC, AI Engine, Clocking wizard, interrupt controller
- Interface blocks: High-speed I/Os, memory controllers
- Map RTL modules that interact with AI Engine through streaming or memory mapped interfaces and other platform streaming interfaces to Vitis RTL kernels
Following are the benefits of this approach:
- Ensures the platform is highly reusable
- Promotes separation of tasks
- Improves the ability to automate the integration process
- Increases scope and opportunity for DFX