Using the Vitis Environment in the Design Flows - Using the Vitis Environment in the Design Flows - 2026.1 English - UG1273

Versal Adaptive SoC Design Guide (UG1273)
Document ID
UG1273
Release Date
2026-06-24
Version
2026.1 English

The Vitis environment includes tools, libraries, and IP.

  • These let you program, run, and debug the different elements of a Versal adaptive SoC application.
  • These elements include AI Engine kernels and graphs.
  • They include programmable logic (PL) functions.
  • They include software applications running on the processing system (PS).

The Vitis tools use a platform-based approach. They divide the system into the following elements for parallel development and testing:

  • Platform
  • Adaptable subsystem
  • Software application

The following figure shows the elements used in this platform-based approach.

Figure 1. Custom Platform, Adaptable Subsystem, and Software Application

Platforms

Platforms provide the foundational hardware IP blocks and software features for building/integrating adaptable subsystems and software applications. Platforms comprise two parts: the hardware platform and the software platform. The hardware platform contains foundational Versal hardware IP blocks. These include the CIPS/PS Wizard, NoC, I/O controllers, AI Engine array, and other user-specified IP blocks. The software platform defines the domains, device tree, and OS.

The platform insulates application developers from the low-level infrastructure details. Developers can focus on creating adaptable system, such as the software, AI Engine graph, or PL kernel logic. The Vivado tools create the hardware side of the platforms. PetaLinux or Yocto creates the software side of the platforms.

Adaptable Subsystems

Adaptable subsystems perform well-defined functions, leveraging PL blocks and AI Engine graphs (for devices that include AI Engines). PL blocks, commonly called PL kernels, are part of the adaptable subsystems. PL kernels can be RTL, Vivado IP, or high-level synthesis (HLS) blocks.

Developers write dataflow graph specification in C++ to develop the AI Engine program. Developers individually design and verify the different components of an adaptable system. Then, they assemble and integrate these components with a platform using the Vitis linker.

Software Application

The software application runs on the PS and performs high-level application tasks while interacting with the adaptable subsystem. The Vitis embedded software development flow develops the software application.

Vitis Tools

The following Vitis tools support the creation, verification, and integration of the different elements of the complete system:

AI Engine tools
Program, simulate, and debug AI Engine programs. This suite of tools include the aiecompiler, AI Engine simulator (aiesimulator), and x86 simulator (x86simulator).
Vitis HLS
Creates PL kernels from C/C++ source code.
Vivado IP packager
Packages existing IP or RTL code into Vitis PL kernels.
Vitis linker
Integrates AI Engine graphs and PL kernels with a platform.
Vitis packager
Integrates the PS components of the system (the software application) and generates the boot image.
Vitis emulation flow
Simulates the behavior of PS, PL, and AI Engine components. This occurs after integration with the Vitis linker and prior to running on actual hardware.
Vitis analyzer
Provides reports generated during compilation, link, and execution of the system created using the Vitis tools.
Vitis embedded software development flow (with the system software stack including PetaLinux)
Provides support for the PS domain of the embedded processor.
Note: Model Composer is also available if you are familiar with MATLAB® software. For more information, refer to the Vitis Model Composer User Guide (UG1483) and the Vitis Model Composer Examples and Tutorials.

For more information about these tools, refer to the Vitis Unified Software Platform Documentation Landing Page (UG1416).