UltraRAM Primitives - UltraRAM Primitives - 2026.1 English - UG1273

Following is the UltraRAM primitive in Versal adaptive SoCs. To force Vivado synthesis to infer the UltraRAM, set the RAM_STYLE = "ultra" attribute on the RAM.

Extra Registers

In addition to the optional output registers, the UltraRAM supports input registers on the data lines. As with block RAMs, you can reset the optional registers either with synchronous or asynchronous reset signals.

RAM Initialization

You can initialize UltraRAMs to a non-zero value in Versal adaptive SoCs. Initialize the UltraRAMs using the INIT_xx attribute on the RAM for the following languages:

• Verilog: Use the readmemh command.
• VHDL: Set up a function to read an external file in VHDL.

For details, refer to the Vivado Design Suite User Guide: Synthesis (UG901).

Byte Write Enables

The UltraRAM also supports byte write enable operations. As with block RAMs, the bytes can either be 8 bits or 9 bits using the extra parity bit. However, when using byte write with Versal adaptive SoCs, read operations are ignored during writing. When describing UltraRAMs with byte write, the system supports only NO_CHANGE mode.

Asymmetric UltraRAMs

Versal adaptive SoC UltraRAMs support asymmetric aspect ratios. For examples on how to code asymmetric RAMs, refer to this link in the Vivado Design Suite User Guide: Synthesis (UG901).

XPM Inference

XPMs can also infer UltraRAMs. The advantage of using this approach is that XPMs always use the correct coding style for any required RAM type. For more information on XPMs, refer to the Vivado Design Suite User Guide: System-Level Design Entry (UG895).