The Versal adaptive SoC provides system monitoring capabilities similar to UltraScale+ devices. In UltraScale+ device designs, you instantiated the SYSMON IP on the PL side and used the System Management wizard to set up the register configuration for instantiation in the hardware description language (HDL).
To migrate your design, you must manually remove the SYSMON IP from the design. In Versal adaptive SoC, you enable the system monitor features in the CIPS/PS IP Configuration wizard. Memory mapped registers replace dynamic reconfiguration port (DRP) access. For more information, see the Versal Adaptive SoC System Monitor Architecture Manual (AM006).