When you migrate designs to AMD Versal™ adaptive SoC from the AMD UltraScale™ or AMD UltraScale+™ architectures, the AMD tools can only automatically migrate some of the PL primitives and integrated IP blocks. In some cases, there is no equivalent functionality or connectivity in AMD Versal™ devices. Although partial migration can be possible, this approach generally leads to sub-optimal hardware and application performance. Therefore, AMD recommends using the following steps instead:
- Rearchitect any high-bandwidth connections between major blocks to use the NoC instead of the PL-based AXI Interconnect or similar IP.
- Reduce PL logic by leveraging all new integrated blocks, such as the integrated memory controller, DMA, and AI Engine.
- Replace instantiated PL primitives from previous architectures with the equivalent RTL descriptions or XPMs (for example, memory blocks, DSPs, carry logic, multiplexers, and so on).
- Regenerate or recreate all IP blocks.
- Resynthesize the complete design instead of migrating netlists created for previous architectures.
Carefully review any automatically migrated design portion. This ensures the application meets its performance, resource, and power requirements. For designs migrated from AMD Zynq™ UltraScale+™ MPSoCs, AMD recommends recreating the PS functions and connectivity by instantiating the CIPS/PS Wizard IP in a new design. This is instead of attempting migration via tools automation.
The following table shows the blocks and functionality for which automatic migration is available.
| Block | Automated |
|---|---|
| Configurable logic block (CLB) | Yes |
| On-chip memory (OCM) resources (block RAM and UltraRAM) | Most |
| DSP | Yes |
| Clocking | Some |
| I/O | Some |
| Soft memory controllers | No |
| AXI Interconnect | No |
| GT | No |
| PCIe subsystems | No |
| Ethernet MAC | No |
| Processor and peripherals | No |
| System debug | No |
| System monitor (SYSMON) | No |
| Power and error handling | No |
| Security | No |
| Boot and configuration | No |
| PL configuration and JTAG | No |
When migrating designs from AMD Kintex™ UltraScale™ , Kintex UltraScale+, AMD Virtex™ UltraScale™ , or Virtex UltraScale+ devices, you must add the CIPS/PS Wizard IP to enable essential functionality such as device configuration and hardware debug, even if you do not use PS features. Designs migrating from Zynq UltraScale+ MPSoCs are expected to already include a PS block. For more information about the CIPS/PS Wizard IP, refer to the following documents: