System Debug - System Debug - 2026.1 English - UG1273

Debugging designs in PL fabric is similar to previous architectures, but there are several key differences:

• All fabric debug IP cores have AXI4-Stream slave control interfaces. Previous architectures used a proprietary interface standard.
• The AXI-Debug Hub IP core has AXI4-Stream control interfaces for connection to fabric debug IP cores. It also has an AXI4-Memory Map slave interface for connection from the host. The Debug Hub IP used in previous architectures relied on proprietary interfaces for connection to the debug cores and host.
• The debug flows in the Vivado tools now support both automated and manual connectivity between debug hub and debug cores.
• The Versal adaptive SoC architecture no longer offers the JTAG-to-AXI soft debug IP as an option. The DAP and DPC can access AXI-based blocks in your design.
• The AXI4-Stream-based integrated logic analyzer (ILA) core supports both ILA and System ILA functionality. Previous architectures offered these as separate IP cores.
• The AXI4-Stream-based ILA core supports selection of block RAM or UltraRAM as the trace storage memory.
• Versal adaptive SoC architecture no longer offers PJTAG as an option. Instead, a single JTAG interface must be used to access DAP and TAP. Check your debugger vendor for support.

When migrating, consider the following:

Vivado IP integrator

You must manually remove or replace previously instantiated legacy debug cores. Replace the legacy debug cores with the new AXIS-ILA cores in the block design using IP integrator.

Netlist

Xilinx design constraints (XDC) commands for inserting ILA cores into the synthesized design automatically migrate to the new AXIS-ILA debug IP.

RTL

There are new interface requirements. As a result, fabric debug cores from previous architectures do not automatically migrate to the new AXI4-Stream-based debug IP cores. If you instantiate debug cores from previous architectures in the design, you must manually recustomize, regenerate, and reinstantiate the new debug IP.

IBERT and Soft Memory Controller Calibration

The integrated bit error ratio test (IBERT) IP functionality is part of the GT blocks. It can be used with any design that uses the transceivers. Memory controller calibration debug is available for both DDR memory controller blocks and for fabric-based soft memory controller IP.

Debug Hub

New interface requirements automatically insert the legacy Debug Hub into the netlist. This happens only if you enable pl0_resetn in the CIPS/PS Wizard. Alternatively, you can manually add an AXI4 Debug Hub. For details, refer to this link in the Vivado Design Suite User Guide: Programming and Debugging (UG908).