The Vitis hardware emulation flow is the simulation-based method for verifying the adaptable subsystem. Hardware emulation provides detailed visibility into all the elements of the co-simulated system (AI Engine, PS, and PL). You can set breakpoints in the source, trace variables, and plot waveforms for any signal in the PL region of the system. This makes hardware emulation a useful debug platform to track down the root cause of any potential integration issues.
Hardware emulation uses these tools to simulate each element, allowing gradual assembly and verification of the subsystem:
- AI Engine simulator (aiesimulator) for the AI Engine graph
- Vivado simulator or a supported third-party simulator for the RTL behavioral models of the PL
- AMD Quick Emulator (QEMU) for the software code executing on the PS
- Python, C/C++, or HDL traffic generators model data from external I/Os or replace missing functionality with stubs
You must meet performance requirements in hardware emulation, but doing so does not guarantee results. Hardware emulation must meet performance requirements, but this does not guarantee results. Hardware emulation is cycle approximate and therefore, performance results are not final at this stage.
For more information on how to assemble and simulate the adaptable subsystem, refer to the System Simulation section. It is part of the Versal Adaptive SoC Design Process Hubs: System Integration and Validation.