Segmented Configuration enables booting the processors in a Versal device and access DDR memory before the programmable logic (PL) is configured. The boot image allows DDR-based software like Linux to boot first. Then the PL can configure via any primary or secondary boot device or through a DDR image store. Segmented Configuration provides the Versal boot sequence with flexibility similar to that of PL configuration on Zynq UltraScale+ MPSoCs.
This solution uses a Vivado tool
flow for implementation. The only additional annotation required is identifying NoC path
segments included in the initial boot image. This occurs automatically after the project
property enabling the feature is set. Programming image generation (write_device_image) automatically splits the programming
images into two PDI files to be stored and delivered separately. The entire PL is
dynamic and can be completely reloaded while any operating system and DDR memory access
remain active.
For Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 architectures, Segmented Configuration is the only methodology presented – all programming images are generated in two parts so you can boot the processing system independent of the programmable logic. AMD provides additional documentation that clearly declares the resources and features available after the initial boot of the device. This requires the PL to reach full functionality. You have the option to generate a single PDI to load the entire device from a single boot device, but the PDI remains internally segmented and brings up the device in stages.
For more information on Segmented Configuration, including design requirements and a tutorial walk-through, refer to the Segmented Configuration documentation. It is available from the AMD Vivado GitHub repository.