Segmented Configuration - 2024.2 English - UG1273

Versal Adaptive SoC Design Guide (UG1273)

Document ID
UG1273
Release Date
2024-11-20
Version
2024.2 English

Segmented Configuration is a solution that enables you to boot the processors in a Versal device and access DDR memory before the programmable logic (PL) is configured. This allows DDR-based software like Linux to boot first followed by the PL, which can be configured later if needed via any primary or secondary boot device or through a DDR image store. The Segmented Configuration feature is intended to present the Versal boot sequence with similar flexibility to configure PL as can be done with Zynq UltraScale+ MPSoCs.

This solution uses a standard Vivado tool flow through implementation, with the only additional annotation required being the identification of NoC path segments to be included in the initial boot image. This occurs automatically after the project property enabling the feature has been set. Programming image generation (write_device_image) automatically splits the programming images into two PDI files to be stored and delivered separately. The entire PL is dynamic and can be completely reloaded while any operating system and DDR memory access remain active.

For more information on Segmented Configuration, including design requirements and a tutorial walk-through, see the Segmented Configuration tutorial available from the AMD Vivado GitHub repository.