The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 12/03/2025 Version 2025.2 | |
| General updates | Minor updates throughout document. |
| Series Comparison | Updated PCIe generation term. |
| CIPS | Updated introduction description. |
| Processing System Wizard | Updated introduction description. |
| Connectivity Peripherals | Updated PCIe generation term. |
| Report Power | Updated description. |
| Design Closure | Updated DRC description. |
| GT | Added GT Wizard subsystem description. |
| 05/29/2025 Version 2025.1 | |
| General updates | Added Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 content throughout document. |
| DDR Memory Controller for DDR5, LPDDR5, and LPDDR5X | Added section. |
| Segmented Configuration | Link update. |
| Tandem Configuration | Updated Tandem formatting description. |
| AXI Interconnect | Updated description to add Modular NoC. |